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| publication number s75ws-n_02 revision a amendment 1 issue date september 8, 2005 s75ws-n based mcps stacked multi-chip product (mcp) 256 megabit (16m x 16-bit) cmos 1.8 volt-only simultaneous read/write, burst-mode flash memory with 128 mb (8m x 16-bit) ram type 4 and 512 mb (32m x 16-b it) data storage data sheet preliminary september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps ii preliminary notice on data sheet designations ! "# $ % $ " & % " % # $ ! % $ % " ' ! " # $ % ( ) ! " % ! "' " * ' % ! + " ' % " % ( ) % * " " # $ % , " " " !! #!- . + / ' 0 $1 ! % ! " ( ) ! % + 2" * 3 #4 , 5 publication number s75ws-n_02 revision a amendment 1 issue date september 8, 2005 general description 67.%/ ' 4 %! 4! ' " ( 1 89.%/ , :#4 ; 1 89.%/, "( distinctive characteristics ! "" #$%&#$'(& ) * < 7;42& ==4& >? 42& + <9+@8 >;,ab# 1 < . c87d!e>7d! s75ws-n based mcps stacked multi-chip product (mcp) 256 megabit (16m x 16-bit) cmos 1.8 volt-only simultaneous read/write, bu rst-mode flash memory with 128 mb (8m x 16-bit) ram type 4 and 512 mb (32m x 16-bit) data storage data sheet preliminary device code flash density ram density data flash density 256 mb 128 mb 512 mb 67.87=/ , september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 2 preliminary contents s75ws-n based mcps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i 1 product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 connection diagrams/physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 special handling instructions for fbga pa ckage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 connection diagram C ram type 4-based pi nout, 9 x 12 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 physical dimensions C fea084 C fine pitch ball grid array 9 x 12 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 s29ws-n mirrorbit tm flash family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 input/output descriptions & logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 product overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.2 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.3 synchronous (burst) read mode & configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.3.1 continuous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.3.2 8-, 16-, 32-word linear burst read with wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.3.3 8-, 16-, 32-word linear burst without wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.3.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.4 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.5 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.5.1 single word programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.5.2 write buffer programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.5.3 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.5.4 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.5.5 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.5.6 program suspend/program resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.5.7 accelerated program/chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.5.8 unlock bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.5.9 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.6 simultaneous read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.7 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.8 handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.9 hardware reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.10 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2 persistent protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.3 dynamic protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.4 persistent protection bit lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.5 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.6 advanced sector protection software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.7 hardware data protection methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.7.1 wp# method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.7.2 acc method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.7.3 low v cc write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.7.4 write pulse glitch protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.7.5 power-up write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 preliminary 12 power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 12.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.2 automatic sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.3 hardware reset# input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13 secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.1 factory secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2 customer secured silicon sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.3 secured silicon sector entry/exit command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14.3 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14.4 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14.5 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14.6 v cc power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14.7 dc characteristics (cmos compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 14.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14.8.1 clk characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14.8.2 synchronous/burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.8.3 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.8.4 ac characteristicsasynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.8.5 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.8.6 erase/program timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.8.7 erase and programming performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 14.8.8 bga ball capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 15 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 15.1 common flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 16 commonly used terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 1.8v psram type 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 17 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 18 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 19 power up and standby mode timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 19.1 power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 19.2 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 20 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 21 mode register setting operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1 21.1 mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 21.2 mrs pin control type mode register setting timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 22 asynchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 22.1 asynchronous 4 page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 22.2 asynchronous write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 22.3 asynchronous write operation in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 23 synchronous burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 23.1 synchronous burst read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 23.2 synchronous burst write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 24 synchronous burst operation terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 24.1 clock (clk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 24.2 latency count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 24.3 burst length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 24.4 burst stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 24.5 wait control (wait#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 24.6 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 25 low power features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 25.1 internal tcsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 4 preliminary 25.2 driver strength optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 25.3 partial array refresh (par) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 26 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 27 dc recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 28 capacitance (ta = 25c, f = 1 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 09 29 dc and operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 0 29.1 common . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 30 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 30.1 test conditions (test load and test input/output reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 30.2 asynchronous ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 30.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 30.3.1 asynchronous read timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 30.3.2 asynchronous write timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 30.3.1 asynchronous write timing waveform in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 31 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 31.1 test conditions (test load and test input/output reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 31.2 synchronous ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 31.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 31.3.1 synchronous burst operation timing wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 31.3.2 synchronous burst read timing waveform s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 31.3.3 synchronous burst read stop timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 31.3.4 synchronous burst write stop timing wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 31.3.5 synchronous burst read suspend timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 32 transition timing waveform between read and write . . . . . . . . . . . . . . . . . . . . . . . . . . .131 33 revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 preliminary ta b l e s 8@ 4!! 0! @? f@ $ g1 @@ =@ $ g1 @= 9@ 89.87=/ h4 # 4 @9 @?@ 1 8@ @?8 # 89.87=/ 8f @?f # 89.@8>/ 8f @?; # ga ! 89.87=/i>?42& 8f @?7 # ga ! 89.87=/i==42& 8f @?= # ga ! 89.87=/i7;42& 8; @?6 # ga ! 89.@8>/ 8; @?> a # b 87 @?9 ! : 8= @?@? # # 86 @?@@ # - 86 @?@8 # -+ 8> @@@ ': 7@ @@8 76 @f@ # =? @;@ =; @;8 . : => @7@ 4 #! >6 8?@ # ; : h# . 4 #@7g#@;j?g? 99 8?8 a : h# . 4 #@7g# @;j?g@ 99 8?f a : h a . 4 #@7g#@;j@g?@ ?? 8@@ 4 : # , , @?@ 8@8 4 : @?@ 8@f 4:#!! @?8 8;@ ! @?7 8;8 / ! '@ @?7 8;f a @?6 87@ #:4 ! @?> f?@ # : #!! @@8 f?8 # : #!! @@f f?f # . #!! @@; f?; # . #!! kalh al! @@7 f?7 # . 4 #!! @@= f?= # . 4 #!! @@6 f?6 # . 4 #!! @@> f?> # . 4 #!! @@9 f@@ a 1 #!! @88 f@8 a : #!! @8f f@f a : #!! @8; f@; a : #!! @87 f@7 a . #!! @8= f@= a . #!! @86 f@6 a : #!! @8> f@> a . #!! @89 f@9 a : #!! @f? f8@ a : # . # #!! @f@ f88 a : # . "# 0l #!! @f8 f8f # . # a : #!! @ff f8; # . "# 0l a : #!! @f; f87 # . "# 0l a : #!! @f7 f8= # . "# 0l a : #!! @f= september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 6 preliminary figures , ;@ 4!a ' @ @8 , 6@ 89.%/a ' @6 , @?@ g# 88 , @?8 : 8; , @?f . f? , @?; . a 1 f; , @?7 - 1 f= , @?= . 1 ," ;f , @@@ # gk 7? , @@8 a g- # 7f , @@f ': # 7= , @;@ 4+ / 1 . =f , @;8 4+ 1 . =f , @;f =; , @;; $ . 4 =7 , @;7 0 !! " % =7 , @;= ! m! & =6 , @;6 ! m a 4 : =9 , @;> >%" a ".# 6? , @;9 >%" a " .# 6? , @;@? a ": n 1 ! a 6@ , @;@@ # 4 : 68 , @;@8 : 6f , @;@f !g - 1 67 , @;@; 1 k #0 l 6= , @;@7 1 k ! m : #0 l 66 , @;@= # k 'a 6> , @;@6 l - # 6> , @;@> a - # 69 , @;@9 g a 69 , @;8? 38 3= >? , @;8@ "a ! " , o==42& >? , @;88 "a ! g- a ' >@ , @;8f -+ . $ >8 , @;8; a '%%a ': g. ! >f , @9@ " k 9> , @98 4 4 9> , 8@@ 4 : 1-lj0 $2 @?8 , 88@ # ;% : @?f , 888 # . @?f , 8f@ a : @?; , 8f8 a . @?; , 8;@ ! : @?7 , 8;8 .#$l : g. ! @?= , 87@ #:4 -+ -+ @?> , f?@ #:4 -+ -+ @@? , f?8 . 1# : ! @@8 , f?f . 1 : ! @@f , f?; . 1. ! @@; , f?7 . . ! 8 @@7 , f?= . 1. ! # @@= , f?6 . 1. ! "# 0l @@6 , f?> . 1. ! "# 0l @@> , f?9 . 14 . ! "# 0l @@9 7 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 preliminary , f@@ #!1 ! @8? , f@8 . 1a a 1 @88 , f@f . a : ! @ @8f , f@; . a : ! 8 @8; , f@7 . a : ! f @87 , f@= . a . ! @ @8= , f@6 . a . ! 8 @86 , f@> . a : !l @8> , f@9 . a . !l @89 , f@@? . a : ! @ @f? , f8@ a : # . # @f@ , f88 a : # . "# 0l @f8 , f8f # . # a : @ff , f8; # . "# 0l a : @f; , f87 a : a . @f7 , f8= a . a : @f= september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 8 preliminary 1 product selector guide device model numbers mcp configuration code density (mb) ram density (mb) data flash density (mb) flash speed (mhz) psram speed (mhz) dyb power-up state ( see note ) psram (ram type 4) supplier package 84 ball fbga (mm) code flash ram (mb) data storage flash 67.87=/ , m .87=/ @8> 8+.87=/ 87= @8> 7@8 7; 7; ? ;9+@8 /m @ p == == ? /p @ 2 >? >? ? /2 @ 9 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 preliminary 2 ordering information " ( ! " !"# " 67 " $ #" ! " !% & & 0! ! ' " s75ws 256 n d f ba w l k 0 + ," ?j 8 j 6* : fj@f* : -"" .-" m j :#4 ; 7;42& p j :#4 ; ==42& 2 j :#4 ; >?42& + / . 0/! 1". * - j @; 9+@8 >;q ? / j @; 9+@8 >;q @ ," . j . c87d!e>7d! + ," a# j 0 , % ab#ab# % ! ' a, j 0 , % ab#ab# % ' * , j 7@848+87=4 j @8>4 ,* / j @@? 4a * 87= j 87=4 67.j 4 % 4! @>% a 4 ,4 :#4 table 2.1 mcp configurations and valid combinations valid combination 67.87=/ , a# a, . / m 2 september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 10 preliminary 3 input/output descriptions f @ ' table 3.1 input/output descriptions symbol description # + c#? # $ ! 3@7% 3? $ g1 1-l 1 - .-l . - 0 b /! /! q : n : $ a , ! m ! ' $ " ! m 0 $ 0 $2 " ! #0 l # 0 $ , ,%:l 2" ,%.l 2" " #0 $ 0 $2 ,%#!! # #0 22 q ' #0 $ 0 $2 :%!-l !% :#4 ,@%!-l !% ! , # ! ma 4 ,8%!-l !% ,@ ,8%!-l !% ,8 :%4:l ! : - :#4c:#4 ; ,%0 !! ,@>0% " :%0 !! :#4" :%kal k a ! :#4 :% al " a ! 11 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 preliminary 4 mcp block diagram & '("#$ # "( '$ )& *& +,- +,-* +,-. " % "# "# # " /# 0" # # "0 $& figure 4.1 mcp block diagram 1 a0-a22 a0-a22 a23 a23 rdy rdy dq0-dq15 cl k clk avd# avd# f1-ce# ce# oe# oe# f-rst# reset# vss vss f-acc acc f1-wp # wp# f-we # we# vcc f-vcc vccq f-vccq a0-a22 wait# clk avd# r-ce# ce# oe# r-lb # lb# r-ub# ub# we# r-mrs# mrs# vss vcc r-vcc vccq r-vccq a0-a22 a23 rdy clk avd# f2-ce# ce# oe# reset# acc fd-wp # wp# we# vss vcc vccq a0-a22 a23 rdy clk avd# f3-ce# ce# oe# reset# acc wp# we# vss vcc vccq dq0-dq15 dq0-dq15 dq0-dq15 dq0-dq15 ws256n flash memory 128mb memory ws256n flash memory ws256n flash memory v september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 12 preliminary 5 connection diagrams/physical dimensions $g1 ' 67. 5.1 special handling instruc tions for fbga package , 4 ,ab# ' , ,ab# ' + % ' g ' + @7?d! 5.2 connection diagram C ram ty pe 4-based pino ut, 9 x 12 mm dnu dnu m10 legend: dnu dnu b2 adv# vss b3 b4 clk f-vcc b6 c5 d5 rfu b7 rfu b8 rfu b9 b 9 rfu b5 f1-wp# c2 a7 c3 c3 c 3 c 3 r-lb# c4 we# c6 a8 c7 a11 c8 f2-ce# c9 f-acc a3 d2 a6 d3 r-ub# d4 rfu d6 a19 d7 d7 d 7 d 7 a12 d8 d8 d 8 d 8 a15 d9 d9 d 9 d 9 f-rst# a2 e2 a5 e3 a18 e4 a20 e6 a9 e7 a13 e8 a21 e9 rdy e5 a1 f2 a4 f3 a17 f4 a23 a10 f7 a14 f8 a22 f9 rfu f5 a0 g2 vss g3 dq1 g4 rfu g6 dq6 g7 rfu g8 a16 g9 rfu g5 f1-ce# h2 oe# h3 dq9 h4 dq4 h6 dq13 h7 dq15 h8 r-mrs# h9 dq3 h5 r-ce1# j2 dq0 j3 dq10 j4 r-vcc j6 dq12 j7 dq7 j8 vss j9 f-vcc j5 rfu k2 dq8 k3 dq2 k4 rfu k6 dq5 k7 dq14 k8 fd-wp# k9 dq11 k5 rfu l2 rfu l3 vss l4 f3-ce# l6 rfu l7 f-vccq l8 dnu l9 f-vcc l5 x x x x x x x x x x x x x x x x x x x rfu (reserved for future use) data flash shared only flash 2 data only flash 3 data only flash 1 code only ram only all shared all flash shared only do not use a1 a10 f6 m1 13 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 preliminary 5.3 physical dimensions C fea084 C fine pitch ball grid array 9 x 12 mm 3423 \ 16-038.21a package fea 084 jedec n/a d x e 12.00 mm x 9.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.10 --- --- ball height a2 1.11 --- 1.26 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10 e1,e10,f1,f10,g1,g10 h1,h10,j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view 0.15 c a b m c m 0.08 publication number s75ws-n_02 revision a amendment 1 issue date september 8, 2005 general description 89.87=g@8> 4 , @@? , " "& " % ' >?42& 0 !! @60@970 ' r " % " " distinctive characteristics - #$2& 3" 3 #$%45#$'(& ##4 /6,* - 37 " !*8 9:;! 7 / -<; + * #=32 ! 7-:(=3#:2> " #=?! *" :(@3#:==@?! 7-:(=3#:2 23#=39: !* !* ! " - -- #:2 ! * :4; " a #44> 444 " " 0" " !*ba a @:$@ ) ! 7c " " " d!& ! * ! * - 7 " " " " - " a " 1+/" " " -* * " " > " "" " -"" * performance characteristics s29ws-n mirrorbit tm flash family s29ws256n, s29ws128n 256/128 megabit (16/8 m x 16 bit) cmos 1.8 volt-only simultaneous read/write, burst-mode flash memory 128 mb flash advance information data sheet 256 mb flash preliminary , -" e" )8 24==(@ 4+ $#!! >?>?>? 4+ a # a#!! 9 @@8 @f7 4+# # #!! >?>?>? 4+!-l# !- >?>?>? 4+1-l# 1- @f7 @f7 @f7 " " ! a : i>?42& f> # 1 7? # @9 # - @9 # 4 8?s# ," fa , . ;?s - . a 0 !! . 9;s - . a 0 #!! . =s - @=m" @7? - =;m" =?? 15 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary 6 input/output descriptions & logic symbol =@ ' table 6.1 input/output descriptions symbol type description #8fc#? $ # .87=/#88%#?.@8> 3@7c 3? $g1 g !-l $ !- # ! m 1-l $ 1 - # ! m .-l $ . - 0 !! " 0 $g1 b /! /! / : n 1 : $ " ! m $ ! '$ $ " ! m 0 $ 0 $2 " #0 l $ # 0$ . " q" " + ' . :--l $ 2" : "j .l $ . #0 $ 0 $2 #!! $ # $ #0 22 q ' #0 $ 0 $2 :,k : : 4!'% "4! september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 16 advance information/preliminary 7 block diagram figure 7.1. s29ws-n block diagram $ g1 a t% n% !- 1 - - 0 b b40 b 0 !! ! ! : 0 !! 0 .-l :--l .l #!! !-l 1-l 3@7 1 3? n%b ! 4+ # # + c#?u : n a : n a ! a # ! #0 l ! m u .87=/(#8f%#? .@8>/(#88%#? 17 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary 8 additional resources 0 """ """ 5 " ( "" k 1 a #4 k a 4 ,4 : g. - g: 4av,4 . a a : %$ . " ! ,$ 0 @;0 -+ -" / ! -! -"" "% - , , -"" 02 0 $a$ 1:!# ,* -"" ! ! ( a k ! (2. i # ( i - 4 - # p ((gg 5 g5g g gl6 g + h h (gg' g (gg 5 g5g g gl6 * k(;?>6;9%76?f p ?f7f88%ff8; -" ddd 9@7 b 1a+f;7f !#9;?>>%f;7f k# (;?>%9=8%87?? @%>==%#/$1/ p ;%ff%;/ 5 ' 5 ' %' ' @=?%??8f (e>@%f%7f?8%88?? , (e>@%f%7f?8%8=6; (gg""" september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 18 advance information/preliminary 9 product overview 89.%/ 87= @8>4 @> % g" , & r" "" & @=>4"@= >% @=% f8%" "" " " f8%" % " g # ( # 87=" 1 9.1 memory map 89.87=g@8>/4 @= ' & " 9 @ c 98 "#% #% # #2# 3 "!" " 0" #" & # " ## # 4" "$"# # # 51 6 0 # #" " ## #! #! # # # #"7 &/ 4! *89 # #0 44144////& table 9.1 s29ws256n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 84a ; f8 ? #??? ??????c??f,,, ! #??@ ??;???c??6,,, #??8 ??>???c??a,,, #??f ??!???c??,,,, @7 @8> #??;#?@> ?@????c?@,,,,?,????c?,,,,, #@8>ma ++????c++,,,, 84a @= @8> @ #?@9#?f; @?????c@?,,,,@,????c@,,,,, 84a @= @8> 8 #?f7#?7? 8?????c8?,,,,8,????c8,,,,, 84a @= @8> f #?7@#?== f?????cf?,,,,f,????cf,,,,, 84a @= @8> ; #?=6#?>8 ;?????c;?,,,,;,????c;,,,,, 84a @= @8> 7 #?>f#?9> 7?????c7?,,,,7,????c7,,,,, 84a @= @8> = #?99#@@; =?????c=?,,,,=,????c=,,,,, 84a @= @8> 6 #@@7#@f? 6?????c6?,,,,6,????c6,,,,, 84a @= @8> > #@f@#@;= >?????c>?,,,,>,????c>,,,,, 84a @= @8> 9 #@;6#@=8 9?????c9?,,,,9,????c9,,,,, 84a @= @8> @? #@=f#@6> #?????c#?,,,,#,????c#,,,,, 84a @= @8> @@ #@69#@9; a?????ca?,,,,a,????ca,,,,, 84a @= @8> @8 #@97#8@? !?????c!?,,,,!,????c!,,,,, 84a @= @8> @f #8@@#88= ?????c ?,,,, ,????c ,,,,, 84a @= @8> @; #886#8;8 -?????c-?,,,,-,????c-,,,,, 84a @7 @8> @7 #8;f#876 ,?????c,?,,,,,-????c,-,,,, ; f8 #87> ,,????c,,f,,, ! #879 ,,;???c,,6,,, #8=? ,,>???c,,a,,, #8=@ ,,!???c,,,,,, 19 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary "#% #% # #2# 3 "!" " 0" #" & # " ## # 4" "$"# # # 51 : 0 # #" " ## #! #! # # # #"7 &/ 4! *89 # #0 44144////& table 9.2. s29ws128n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes @4a ; f8 ? #??? ??????c??f,,, ! f8 #??@ ??;???c??6,,, f8 #??8 ??>???c??a,,, f8 #??f ??!???c??,,,, 6 @8> #??;#?@? ?@????c?@,,,,?6????c?6,,,, #@8>ma ++????c++,,,, @4a > @8> @ #?@@#?@> ?>????c?>,,,,?,????c?,,,,, @4a > @8> 8 #?@9#?8= @?????c@?,,,,@6????c@6,,,, @4a > @8> f #?86#?f; @>????c@>,,,,@,????c@,,,,, @4a > @8> ; #?f7#?;8 8?????c8?,,,,86????c86,,,, @4a > @8> 7 #?;f#?7? 8>????c8>,,,,8,????c8,,,,, @4a > @8> = #?7@#?7> f?????cf?,,,,f6????cf6,,,, @4a > @8> 6 #?79#?== f>????cf>,,,,f,????cf,,,,, @4a > @8> > #?=6#?6; ;?????c;?,,,,;6????c;6,,,, @4a > @8> 9 #?67#?>8 ;>????c;>,,,,;,????c;,,,,, @4a > @8> @? #?>f#?9? 7?????c7?,,,,76????c76,,,, @4a > @8> @@ #?9@#?9> 7>????c7>,,,,7,????c7,,,,, @4a > @8> @8 #?99#@?= =?????c=?,,,,=6????c=6,,,, @4a > @8> @f #@?6#@@; =>????c=>,,,,=,????c=,,,,, @4a > @8> @; #@@7#@88 6?????c6?,,,,66????c66,,,, @4a 6 @8> @7 #@8f#@89 6>????c6>,,,,6-????c6-,,,, ; f8 #@f? 6,????c6,f,,, ! f8 #@f@ 6,;???c6,6,,, f8 #@f8 6,>???c6,a,,, f8 #@ff 6,!???c6,,,,, september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 20 advance information/preliminary 10 device operations g" '% , 1 " " @7@ @78 q " + % . " ' " " " 10.1 device operation table @ ? @ table 10.1 device operations ;<; " =<; " ><?+ @ab<@ab& 10.2 asynchronous read # $ # " " % " % # + c #? " #0 l !-l0 $ .-l 0 $2 #0 l 1-l 0 $ #0 l 0 $2 #g 3@7%#g 3? 1- 1-l operation ce# oe# we# addresses dq15C0 reset# clk avd# # : %# 2 #$ 1 2 t # : %# 2 #$ 1 2 t # . 2 #$ $g1 2 t . 2 #$ $g1 2 !-l 2 t t t 2$b2w 2 t t 2" : t t t t 2$b2w t t burst read operations (synchronous) a # t 2 #$ t 2 # a + " a 2t a 1 22 a 2 t 2 t 2$b2w 2 t a :--l t t 2 t 2$b2w t t a " a t2#$ $g1 2 21 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary 10.3 synchronous (burst) read mode & configuration register . 5 " # & ' " % @?f@ @?f8 @?ff " % " 1 ! : " " $#!! " " : n : ! : " @?f; ! : @ 7 @ 4 #! figure 10.1. synchronous/asynchronous state diagram " 5 " ( $#!! ( ' !:@fc!:@@( ' " $#!! " a#!! ' " 5 " ( (" " #x@(?y??# % % " power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (cr15 = 0) set burst mode configuration register command for asynchronous mode (cr15 = 1) september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 22 advance information/preliminary " " " " %% " #x@(?y?@ @? @@ ( @8>" 1 " " ' " ' ( " + 2 " " $ "" : n " + @?8 % @?6 " 89.87=g@8>/ : ! % : !:@@%!:@; ta b l e 1 0 . 2 address latency (s29ws256n) ta b l e 1 0 . 3 address latency (s29ws128n) ta b l e 1 0 . 4 address/boundary crossing latency (s29ws256n @ 80mhz) ta b l e 1 0 . 5 address/boundary crossing latency (s29ws256n @ 66 mhz) 7 7 - ? +" ? @ 8 f ; 7 = 6 > @ +" @ 8 f@" ; 7 = 6 > 8 +" 8 f @" @" ; 7 = 6 > f +" f @" @" @" ; 7 = 6 > 7 7 - ? 7 = 6" ? @ 8 f ; 7 = 6 > @ 7 = 6" @ 8 f @" ; 7 = 6 > 8 7 = 6" 8 f @" @" ; 7 = 6 > f 7 = 6" f @" @" @" ; 7 = 6 > 7 7 - ? 6" ? @ 8 f @" @" ; 7 = @ 6" @ 8 f @" @" @" ; 7 = 8 6" 8 f @" @" @" @" ; 7 = f 6" f @" @" @" @" @" ; 7 = 7 7 - ? =" ? @ 8 f @" ; 7 = 6 @ =" @ 8 f @" @" ; 7 = 6 8 =" 8 f @" @" @" ; 7 = 6 f =" f @" @" @" @" ; 7 = 6 23 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary ta b l e 1 0 . 6 address/boundary crossing latency (s29ws256n @ 54mhz) ta b l e 1 0 . 7 address/boundary crossing latency (s29ws128n) figure 10.2. synchronous read 7 7 - ? 7" ? @ 8 f ; 7 = 6 > @ 7" @ 8 f@" ; 7 = 6 > 8 7" 8 f@"@" ; 7 = 6 > f 7" f @" @" @" ; 7 = 6 > 7 7 - ? 7 = 6" ? @ 8 f @" ; 7 = 6 @ 7 = 6" @ 8 f @" @" ; 7 = 6 8 7 = 6" 8 f @" @" @" ; 7 = 6 f 7 = 6" f @" @" @" @" ; 7 = 6 write unlock cycles: address 555h, data aah address 2aah, data 55h write set configuration register command and settings: address 555h, data d0h address x00h, data cr load initial address address = ra read initial data rd = dq[15:0] read next data rd = dq[15:0] wait x clocks: additional latency due to starting address, clock frequency, and boundary crossing end of data? yes crossing boundary? no yes completed delay x clocks unlock cycle 1 unlock cycle 2 ra = read address rd = read data command cycle cr = configuration register bits cr15-cr0 note: setup configuration register parameters no ( ; $% #& september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 24 advance information/preliminary #4$9$# / $ " ??????" % !-l :--j0 $ ! #0 l" " $ @8>%" % " @?9 $ ' " ' ' k "% #0 l #4$9$: 2;>#=;>9:;7 d / !*7 " $ + "> @= f8" " " & " @?> , + >%" f! " f>%f, " f!%f %f-%f,%f>%f9%f#%fa % " " " $ @=%" f8%" . " ' c ""#! ##" # ## % $ # 0 $*8 2 #d# ""2"# # "# % $ ##" & ta b l e 1 0 . 8 burst address groups #4$9$9 2;>#=;>9:;7 d / !*7 " $" >%" @=%" f8%" + + " > @= f8 " , + >%" f! " f9%;? " f!%f %f-%f,%;?%;@%;8%;f" + " #0 l / @8> " " " " mode group size group address ranges >%" >" ?%6 >%, @?%@6 @=%" @=" ?%, @?%@, 8?%8, f8%" f8" ??%@, 8?%f, ;?%7, 25 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary #4$9$@ " k " % " % + ! : % !-l ! : % @7@ " ta b l e 1 0 . 9 configuration register ( " +" "% & " % % @ 7 @ 1 " / - / !:@7 : 4 ?j : a 4 - @j# : 4 - !:@; : @j89.87=/=6. ?j# (@ )8 == *8 24 )8 !:@f . 89.@8>/ ?@@ ?@@j 7 ! m @??j = ! m @?@j 6 ! m @@?j: @@@j: $ " " / @ 8 89.87=/ !:@8 89.@8>/ @?? 89.87=/ !:@@ 89.@8>/ @?@ 89.87=/ !:@? : n ?j: n " @j: n !:9 : @j !:> : n ?j: n ' @j: n " . !:@f%!:@@ ??? : n " !:> !:6 : @j !:= : @j !:7 : ?j !:; : ?j !:f a .# ?j/.# a @j.# a !:8 !:@ !:? a ???j! ?@?j>%. a ?@@j@=%. a @??jf8%. a # & ( % # &* 3 &6 2"# # e" ! #& *& ( $ # #( "!" " !# .& +" "( "# "#" # 2 3 2 # & september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 26 advance information/preliminary 10.4 autoselect # $ % " # % % . @?@? z " ' " # # ' " + # # # # " " ' % % # " " # " % % '" - @7@ ta b l e 1 0 . 1 0 autoselect addresses description address read data 4 $ a#e?? ???@ $ .@ a#e?@ 886- $ .8 a#e?- 88f?.87=/ 88f@.@8>/ $ .f a#e?, 88?? $ a / a#e?f 3@7% 3>j: 36, 'a(@j ' ?j/ ' 3=! 'a(@j ' ?j/ ' 372 ' a(@j: ?j 2 ' 3; 3f.l a! (??j.l a a a ?@ @? @@j: 38j: 3@ na" x ': 3;y(@jk ' ?j ' 3?a- x ': 3fy(@j- " ?j- a ' 'g k ' #e?8 ???@j ' ????jk ' /f*8c fg) h h # 0 & software functions and sample code table 10.11 autoselect entry , j[# - ! cycle operation byte address word address data k '! @ . a#+### a#+777 ?+??## k '! 8 . a#+777 a#+8## ?+??77 # ! . a#+### a#+777 ?+??9? 27 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary & $# 2"" 0" 2 #& *& < ##& % ##"# e" & .& %# <%# ##& " ! + % $ : #";2; 0 "0 # ?# " """ """ 5 , " /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (uint16 *)bank_addr + 0x000 ); /* read manuf. id */ /* autoselect exit */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* exit autoselect (write reset command) */ table 10.12 autoselect exit , j[# -+! cycle operation byte address word address data k '! @ . ettt ettt ?+??,? september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 28 advance information/preliminary 10.5 program/erase operations " " 2" @?> , " #0 l !-l0 $ 1-l0 $2 " .-l !-l0 $ 1-l0 $2 " " # .-l!-l " @ .-l!-l / " ( . - 36 3=: . 1 #)?* ')@*# 37j@ # " )?*1 )?*)@* # " - # + # !,$ " % #" " " % #4$($# - 7 " $ , " , % >% @=%f8%" . . a % @ 7 @ , @?f " . - % 36 3=: . 1 + # !,$ " 29 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary # " figure 10.3. single word program write unlock cycles: address 555h, data aah address 2aah, data 55h write program command: address 555h, data a0h program data to address: pa, pd unlock cycle 1 unlock cycle 2 setup command program address (pa), program data (pd) fail. issue reset command to return to read array mode. perform polling algorithm (see write operation status flowchart) yes yes no no polling status = busy? polling status = done? error condition (exceeded timing limits) pass. device is in read mode. september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 30 advance information/preliminary # < # ##& " ! + " : #";2; 0 "0 # ?# " """ """ 5 , " /* example: program command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll for program completion */ #4$($: 7 / . a " " + f8" % " )"* . a " " ' " " . a " # " # " )" @* # " " " " " + ) a ,* % + & " / j @, +% = ?7 " " g g )" % % * # % g " %" % % )" % % * # 4#t %#7 )" % % * g " . a )" % % * . a % $ )" % % * #a1: # " # g " g " / . a ) g* # ) a ,* $ " z " % /1 " % software functions and sample code table 10.13. single word program , j[ ! cycle operation byte address word address data k '! @ . a e### a e777 ??## k '! 8 . a e77; a e8## ??77 . a e### a e777 ??#? . .# .# . 31 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary % 1 " " ) a ,* # # g" . a % ) * a " " % 36 3= 37 38 3@ . a " % ) * % g k . a :-# . a #a1:- " ( & )/ * . . %a % . # g " % % ) # * )" * . )! ! * )* % #a1: 3@j@ 36j ##l ) * 3=j1bb - 37j? . a 1 "#a1:- #). %%a %# * " " k 'a / !,$ " . " " " " k " " " . + % " september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 32 advance information/preliminary & # < # ##& *& ;#<;# $ 2" % ! "d " !% 2 #2" !% $ #!$% !g.6& .& /!4"!! " " $ ""# !! 2" % % 2" " #!% 2 #c2 # ##"% & " ! + " : #";2; 0 "0 # ?# " """ """ 5 , " /* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. a flash page begins at addresses */ /* evenly divisible by 0x20. */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (uint16 *)sector_address ) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* all dst must be same page */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *( (uint16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *( (uint16 *)addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)addr + 0x555 ) = 0x00f0; /* write buffer abort reset */ software functions and sample code table 10.14. write buffer program , k j[. a ! [ a ,! cycle description operation byte address word address data @ k ' . a e### a e777 ??## 8 k ' . a e77; a e8## ??77 f . a ! . # ??87 ; . .! . # .! /c@ ! *! #9:! $ 7f= a ./ . # ./ ./ . a , . # ??89 33 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary figure 10.4. write buffer programming operation #4$($9 - a @7@ 4 #! q , @?7 - 1 % - - & # " ,,,, write unlock cycles: address 555h, data aah address 2aah, data 55h issue write buffer load command: address 555h, data 25h load word count to program program data to address: sa = wc unlock cycle 1 unlock cycle 2 wc = number of words ? 1 yes yes yes yes yes no no no no no wc = 0? write buffer abort desired? write buffer abort? polling status = done? error? fail. issue reset command to return to read array mode. write to a different sector address to cause write buffer abort pass. device is in read mode. confirm command: sa = 0x29h wait 4 s (recommended) perform polling algorithm (see write operation status flowchart) write next word, decrement wc: pa data , wc = wc ? 1 reset. issue write buffer abort reset command september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 34 advance information/preliminary # " % -# % % " " -# # " + % -# # - - % ' 3f 3f( - $ % .-l . - - ' / " - - % ' 36 3=g 38 ': . 1 1 - # 2" " $ ' , @?7 : - " ! + : #" ;2; 0 "0 # ?# " """ """ 5 % , " /* example: sector erase command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0030; /* write sector erase command */ software functions and sample code table 10.15. sector erase , j [ - ! cycle description operation byte address word address data @ k ' . a e### a e777 ??## 8 k ' . a e77; a e8## ??77 f ! . a e### a e777 ??>? ; k ' . a e### a e777 ??## 7 k ' . a e77; a e8## ??77 = - ! . # # ??f? 1 . ! !* -a $ 35 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary figure 10.5. sector erase operation no write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. wait 4 s (recommended) perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 yes yes yes yes yes no no no no last sector selected? done? dq5 = 1? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading dq7, dq6 and/or dq2. poll dq3. dq3 = 1? ? each additional cycle must be written within t sea timeout ? timeout resets after each additional cycle is written ? the host system may monitor dq3 or wait t sea to ensure acceptance of erase commands ? no limit on number of sectors ? commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data & % 5& # !! # e & *& # "h."!" # # "! & , @?= september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 36 advance information/preliminary #4$($@ *"a -g ! +% @7@ ' - - " - - & # ,,,, % )! * +" . - - ' % 36 3=g 38: ). 1 * # " 2" % " $ ' " ! + : #" ;2; 0 "0 # ?# " """ """ 5 % , " /* example: chip erase command */ /* note: cannot be suspended */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */ #4$($( a - " 3a . - " % % % - " ' " " % -# % - " software functions and sample code table 10.16. chip erase , j[!- ! cycle description operation byte address word address data @ k ' . a e### a e777 ??## 8 k ' . a e77; a e8## ??77 f ! . a e### a e777 ??>? ; k ' . a e### a e777 ??## 7 k ' . a e77; a e8## ??77 = !- ! . a e### a e777 ??@? 37 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary . - " -# % + % + - # " - " # ' % % ) * : " % 36% 3? 36 3= 38 % : @?87 # % ' % % % 36 3= 5 $ % % # : ). a 1 * )# ! % * " - : ' % ' " " , " : # - " " ! + : 3 #";2; 0 "0 # ?# " """ """ 5 , " /* example: erase suspend command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00b0; /* write suspend command */ " ! + : 3 #";2; 0 "0 # ?# " """ """ 5 , " /* example: erase resume command */ *( (uint16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ software functions and sample code table 10.17. erase suspend , j[- ! cycle operation byte address word address data @ . a '# a '# ??a? table 10.18. erase resume , j[- : ! cycle operation byte address word address data @ . a '# a '# ??f? september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 38 advance information/preliminary #4$($= - " 3 " % ). a * % . " % " # ) z% *" " # % % " $ - $ + " # " " # . + # % )# ! * # : " 36 3= 5 ). 1 * " : ) z * + , " : # " % " ! + : #";2; 0 "0 # ?# " """ """ 5 , " /* example: program suspend command */ *( (uint16 *)base_addr + 0x000 ) = 0x00b0; /* write suspend command */ " ! + : #";2; 0 "0 # ?# " """ """ 5 , " /* example: program resume command */ *( (uint16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */ software functions and sample code ta b l e 1 0 . 1 9 . p r o g r a m s u s p e n d , j[ ! cycle operation byte address word address data @ . a '# a '# ??a? ta b l e 1 0 . 2 0 . p r o g r a m r e s u m e , j[ : ! cycle operation byte address word address data @ . a '# a '# ??f? 39 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary #4$($% 3*"a # " " #!! ,* *"" * #4 " $ $ 87 ! @? ! $ 0 22 k % 'a . a % k 'a / ). %%a %#: * " k 'a f% :-- : 0 22 #!! % ' #!!0 22 #!! 0 22 % #!! q #!! ' 0 $ q#!! 0 $2 #4$($2 1+/" k 'a " 1 % k 'a "" " " ' % )! * " ' ' : k 'a k 'a: + ' "% % ' ' 9? ?? ' " ! + ' + : #";2; 0 "0 # ?# " """ """ 5 , " software functions and sample code table 10.21. unlock bypass entry , j[k 'a- ! cycle description operation byte address word address data @ k ' . a e### a e777 ??## 8 k ' . a e77; a e8## ??77 f - ! . a e### a e777 ??8? september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 40 advance information/preliminary /* example: unlock bypass entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *( (uint16 *)bank_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; #4$($' 7 e" - " 3@ 38 3f 37 3= 36 l 36 " - % - " ' - l .-l % / l " " % % . a : l " " " % % - 36 36 36 - . - 36 36 $ " l 36 +% ' - - # l )?* 36. - % - ' - l )@* 36 " 36 table 10.22. unlock bypass program , j[k 'a ! cycle description operation byte address word address data @ ! . a e+++ a e+++ ??#? 8 ! . # # table 10.23. unlock bypass reset , j[k 'a: ! cycle description operation byte address word address data @ : ! @ . a e+++ a e+++ ??9? 8 : ! 8 . a e+++ a e+++ ???? 41 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary # " l 36 + # ' $ - - 2" 36 " p - - 36 % " 3=% 3?" 1 - 1-l " 36 " 36 - 36 3=% 3? 0 36% ?? " ( @?87 . 1 " l 36 , @?= . 1 ," " l% q , @;@6 l - # " l september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 42 advance information/preliminary figure 10.6. write operation status flowchart start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read3 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error erase operation complete read3= valid data? yes no notes: 1) dq6 is toggling if read2 dq6 does not equal read3 dq6. 2) dq2 is toggling if read2 dq2 does not equal read3 dq2. 3) may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4) write buffer error if dq1 of last read =1. 5) invalid state, use reset command to exit operation. 6) valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) data polling algorithm valid for all operations except advanced sector protection. device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5) 43 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary a$ 3= " - - % " - a$ ' .-l % - - % 3= . 3= # " 3= + # x y $ - - 3= 38 " % . - - 3= . - 3=% 2" 38 " % # 36 36( l $ " 3= + # " 3= % % - % # " ( , @?= . 1 ," q ,% @;@> a - # @?8; @?87 a$ 3= 1-l!-l % " ) a$$* 38 " " 3= " % - - " % a$$ .-l 38 " " a 38 " % % 3= " - " : @?8; 38 3= " ( , @?= ) 3=( a$* , @;@6 c @;8? september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 44 advance information/preliminary table 10.24. dq6 and dq2 indications . 36c 3? " " " % " # " " " $ % 36c 3? " 2" " " 37 37$ " % 5 37" $ $ " 37 37 # % '$ " : ,% @?= . " g ' 3= 38 " " % $ " '$ ' 36 " ! "# $ $ 37 " + k 37 )@ * " )@* 37 )@* " )?*1 )?* ')@*k " + 37 )@*k " % % '" % % if device is and the system reads then dq6 and dq2 " " " " 45 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary % & " $' & # " 3f " $ % . % 3f" )?*)@*$ " -# 3f - ! # " 36 l 3= a$ 3f$ 3f)@ * - - q % + - $ 3f)? * % " ' 3f " % $ 3f ' @ ? 8 7 " 3f ( ) '** +, 3@ " . a " k 3@ )@* . a # : . a % 1 ta b l e 1 0 . 2 5 . write operation status & h5#2" #i?2 ,!% !,!% ,# "# 4 !4 "!!"!" "!"#&( # "h5! "!"& *& h6 h* e" 0" ##2 " ##"!"&( " #%# " "#& .& "0" ## #" !# # & )& h" " # f" b(## " f" !!" "#& 5& 3%" "!# % # f" !!" "#&c h6- " f" !!" " " # 3%h6 * - +& .+" ) "/ 011" + "&& & g& /$ ## # +,-## " 3## "+ ,-!" % e" ## #% ! #% " " # ## "#" h*ahg& status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 (note 4) 4 - # 36l ? /g# / ? - - # ? ? @ /g# 4 / f : " $/0# $ c 2 $/0# $ c 2 $/0# $ c 2 $/0# $ c 2 $/0# $ c 2 $/0# $ c 2 : " / % - 4 / = - % % : - @ / ? /g# /g# / %- - % % 36l ? /g# /g# /g# . a / 7 akn 36l ? /g# /g# ? -+ 36l @ /g# /g# ? #a1: 36l ? /g# /g# @ september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 46 advance information/preliminary 10.6 simultaneous read/write g" " ' % " ' # " ' + , @;8; a '%%a ': g. ! "" " "& : !! % !41! %" % %" % 10.7 writing commands/command sequences . # # " " ! m . # " ! m #0 l " " " #0 l !-l0 $ 1-l0 $2 " .-l !-l0 $ 1-l 0 $2 " " " !-l .-l0 $ 1-l0 $2 " # .-l!-l " @ .-l!-l# 9@ c 98 + '(a ' @ @; =;m" " a '? @7 @=m" =;m" # ) ' * ' ) * $ !!8 ) !! * % " )#!! % * )#!! %# * " 10.8 handshaking ' " " % : n: " !-l . 1-l" % " : n @? ! : $ !:@fc!:@@ ! : " @ ? 9 ! : a> ! : " " : n 47 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary 10.9 hardware reset :--l " . :--l " : g" :--l " . :--l 0 "!41 $ !!; $:--l 0 $ 0 :--l " % " , , @;7 @;@8 10.10 software reset " @ 7 @ " ( @ +# 8 " 37 " " f + 'g ' ; % % " - 7 # < # ##& " ! + : #";2 ; 0 "0 # ?# " """ """ 5 % , " /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; " " ( ' : 1 % " " '" % "" software functions and sample code ta b l e 1 0 . 2 6 . r e s e t , j[: ! cycle operation byte address word address data : ! . a e+++ a e+++ ??,? september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 48 advance information/preliminary $ " ' - " ' % % " # $ ' # " - " ' % % $ 3@ . a " \. a #: \ :-- :-- "' + ' "% ' % x y 49 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary 11 advanced sector protection/unprotection # gk " g" " # " " , @@@ figure 11.1. advanced sector protection/unprotection hardware methods software methods acc = v il ( all sectors locked) wp# = v il (all boot sectors locked) password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit 1,2,3 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 3 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppb) 4,5 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) 6,7,8 6. 0 = sector protected, 1 = sector unprotected. 7. protect effective only if ppb lock bit is unlocked and corresponding ppb is ?1? (unprotected). 8. volatile bits: defaults to user choice upon power-up (see ordering options). 4. 0 = sector protected, 1 = sector unprotected. 5. ppbs programmed individually, but cleared collectively 1. bit is volatile, and defaults to ?1? on reset. 2. programming to ?0? locks all ppbs to their current state. 3. once programmed to ?0?, requires hardware reset to unlock. 3. n = highest address sector. september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 50 advance information/preliminary 11.1 lock register # " " " na " )?* " " % % ' ( ': 4 'a 3@ ': " 4 'a 38 table 11.1 lock register , ' @ 7 8 @ $ " " % ' 8 # ': a! - " " a '? " ' " + f $ ' & ; 1 "4 'a 4 'a % " % 4 'a "4 # " ( @ +#$ & a ' " " " 8 $!" $ & " f & g @@8 c @@= 11.2 persistent protection bits a % , @ - a 8 . a ' + a '? l ' " a f - " ' device dq15-05 dq4 dq3 dq2 dq1 dq0 89.87=/ @ @ @ " 4 'a 4 'a ! a 89.@8>/ k na 'aa ?j " @j " a1 % a ?j#a @j#a- " 4 'a 4 'a a 51 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary ; : " ' a 7 : ' " " " " = #: # 6 #8f%#@;.8 7=/ #88%#@;.@8>/ " > $ a 'a a + % " a 9 a @? -+ + " % " a '? @@ a " a : ! " " , @@8 september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 52 advance information/preliminary figure 11.2. ppb program/erase algorithm 11.3 dynamic protection bits a na a )@*a na ! na % )?* )@* "" % " read byte twice addr = sa0 enter ppb command set. addr = ba program ppb bit. addr = sa dq5 = 1? yes yes yes no no no yes dq6 = toggle? dq6 = toggle? read byte. addr = sa pass fail issue reset command exit ppb command set dq0 = '1' (erase) '0' (pgm.)? read byte twice addr = sa0 no wait 500 s 53 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary @ na )?* )@* . a )@* " na 8 $ na " )@* a @@8 f " $ na " )?* ; $ ' " 7 na ! 2" % ' " , a 'a " % " a a 'a ' a = + a 'a .lj0 $ / a na " #!!j0 22 " #!!j0 $2 11.4 persistent protection bit lock bit a 'a . % )?* 'a " )@* " a a 'a @ /" ' "% q " " % 8 a 'a )?* a 11.5 password protection method " 4 " % 4 =;" ' a 'a$ " " a 'a )?* " + "k ' % " a 'a " a @ "1 % "" "4 ' a 8 " ! )?* )@* )?* % " )?* f ")@*" ; #=;%" " 7 " " = "4 'a =;%" " 6 "4 'a september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 54 advance information/preliminary > " " #@c#? ": " "k ' 9 + " ' @? "k ' @s ' =;% " @@ #+ @s ' =;%" @8 " " " @f # " @; $ " "4 'a " a 'a @7 - " a '?: " ' + a '? " @= $ @6 # " @> na a a ' " na a a ' 55 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary figure 11.3. lock register program algorithm write unlock cycles: address 555h, data aah address 2aah, data 55h write enter lock register command: address 555h, data 40h program lock register data address xxxh, data a0h address 77h*, data pd unlock cycle 1 unlock cycle 2 xxxh = address don?t care * not on future devices program data (pd): see text for lock register definitions caution: lock register can only be progammed once. wait 4 s (recommended) pass. write lock register exit command: address xxxh, data 90h address xxxh, data 00h device returns to reading array. perform polling algorithm (see write operation status flowchart) yes yes no no done? dq5 = 1? error condition (exceeded timing limits) fail. write rest command to return to reading array. september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 56 advance information/preliminary 11.6 advanced sector protection software examples @ @ 8 na a a 'a $ a 'a ' )?* a " a 'a ' )@* " " , @@@ " # 11.7 hardware data protection methods " " ( . .l0 $ ' . #!!0 $ ' " % " " ( ##$%$# 7c * . " .l % gk $ 0 $ .l ) * " %% $ 0 $2 .l " " % " " / .l .l + ##$%$: * + 1 #!! 0 $ table 11.2 sector protection schemes unique device ppb lock bit 0 = locked 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status # ? ? + a # ? ? + a # ? @ @ k # ? @ ? na # @ ? + a # @ ? + a # @ @ ? na # @ @ @ k 57 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary ##$%$9 d!& 7 * . 0 !! 0 m1 " % 0 !! " % " %" g " 0 !! 0 m1 " " 0 !! 0 m1 ##$%$@ 7 ij* k / f 1-l !-l.-l " ##$%$( ! ;1"7 * $.-lj!-lj:--lj0 $ 1-lj0 $2 " .-l " % september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 58 advance information/preliminary 12 power conservation modes 12.1 standby mode . " $ 1-l !41 " !-l :--l 0 !! ]?80 !- $ % " $ !!f ) !! * 12.2 automatic sleep mode & , " " #!! e8? !-l .-l 1-l % " " . " . / " " $ !!= !! !41! % 12.3 hardware reset# input operation :--l " . :--l " : g" :--l " . :--l 0 ]?80 "!41 $ !!; $:--l 0 $ " 0 ]?80 :--l " , % " , 12.4 output disable (oe#) . 1-l 0 $2 59 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary 13 secured silicon sector flash memory region +, - / -/ 87= " @8>" @8>" % # 87 =%" , $ a 36 # ?f " , ' " ! $ a 3= " ! ' " " ( . " + a '? 1 " % " " : # a " " ,, ' ?? : ? ! + ? 1 - ! -+ + 4 " + - % - - table 13.1 secured silicon sector addresses 13.1 factory secured silicon sector , " " , $ a 36 )@* ' -/ " " ( # >. -/ " , ! " ! % a -/ ! % z "" -/ " , ! ' ! sector sector size address range ! @8>" ????>?%????,, , @8>" ??????%????6, september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 60 advance information/preliminary 13.2 customer secured silicon sector ! 3= )?* " & $ % ! , " ( 1 ! ! $ a )@* ! % ' ! ' " ' ' ! % ! % " #!! ' " ! a '@ @7 1 ! ' " -+ : " % ? 13.3 secured silicon sector entry/exit command sequences % - % % -+ ! x ! # + @ 7 @ - ! " " + : # " - #?" -+ " " ! + - + : #";2; 0 "0 # ?# " """ """ 5 , " software functions and sample code 61 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary # < # ##& /* example: secsi sector entry command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0088; /* write secsi sector entry cmd */ # < # ##& /* once in the secsi sector mode, you program */ /* words using the programming algorithm. */ # < # ##& /* example: secsi sector exit command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0090; /* write secsi sector exit cycle 3 */ *( (uint16 *)base_addr + 0x000 ) = 0x0000; /* write secsi sector exit cycle 4 */ table 13.2. secured silicon sector entry , j[ - ! cycle operation byte address word address data k '! @ . a e### a e777 ??## k '! 8 . a e77; a e8## ??77 - ! . a e### a e777 ??>> table 13.3. secured silicon sector program , j[ ! cycle operation byte address word address data k '! @ . a e### a e777 ??## k '! 8 . a e77; a e8## ??77 . a e### a e777 ??#? . .# .# . table 13.4. secured silicon sector exit , j [ -+! cycle operation byte address word address data k '! @ . a e### a e777 ??## k '! 8 . a e77; a e8## ??77 -+! . a e### a e777 ??9? september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 62 advance information/preliminary 14 electrical specifications 14.1 absolute maximum ratings ' c=7d!e@7?d! # "" # c=7d!e@87d! 0 ": b ( #$ $g1 + "/ @ c?700 !! e?70 0 !! / @ c?70e870 #!!/ 8 c?70e970 1 ! ! / f @?? # & '""!!+0 "@ab#"#1&5j&" 0 #""# "# @ab#!$ #j 1*&j " #*#& /" )& & '4"!!+0 "@ab#"#j ++ k&5j&" 0 #""# #!$0 #j ++ k*&j " #*#& /" )&* & *& '""!!+"0 " ++"#3&5j&" 0 #""# ++!$ 0 #j 1*&j " #*#& /" )& &'4"!!+ 0 " ++"#k:&5j 2" !$0 #&5j " #*#& .& c! !$% # "! &" # " "# % # & )& ## #%0 # "# l %# '4"!!(" #m!$ # ! ! 0" &"#"## ##" $d " " 0" # $ ""#%0 # " " " "# "#"# # "#"!" &,4# 0" %# !4"!!" ""# 4 " #!$ 0" "%""$& ""# ! "# 0 "!" *:f*8c&+ ""# 3 ! "# "!"$ *:f*5gc& figure 14.1. maximum negative overshoot waveform figure 14.2. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v 63 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary 14.2 operating ranges 7 7 # # c87d!e>7d! -""& 0 !! 0 e@6?0e@970 b " # " # "!"#% 2 2" ""$ 0" "# & 14.3 test conditions table 14.1 test specifications ""# ! "# 0 "!" *:f*8c&+ ""# 3 ! "# "!"$ *:f*5gc& test condition all speed options unit 1 ! ! 5 f? , $ : , f?i7; ==42& 87i>?42& $ ??c0 !! 0 $ 0 !! g8 0 1 0 !! g8 0 c l device under test figure 14.3. test setup september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 64 advance information/preliminary 14.4 key to switching waveforms & ""# ! "# 0 "!" *:f*8c&+ ""# ! "# "!"$ *:f*5 gc& 14.5 switching waveforms 14.6 v cc power-up & ""# ! "# 0 "!" *:f*8c&+ ""# ! "# "!"$ *:f*5gc& *& *:f*8cnj ++ ! "#oja p# j ++ ! q ja p# 2 # "# e" & figure 14.5. v cc power-up diagram parameter description test setup speed unit 0! 0 !! 4 @ waveform inputs outputs ! 2 ! 2 r! # ! ! k ' " /# ! 2$ 2w v cc 0.0 v output measurement level input v cc /2 v cc /2 all inputs and outputs figure 14.4. input waveforms and measurement levels v cc reset# t vcs 65 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary 14.7 dc characteristics (cmos compatible) & '4"!!@ ++ # "" "# # 2"j ++ <j ++ !4& *& +,-!#% # " 2 ! #" (r"& .& @ ++ "# "#$" $ ##.&5! a'=7 2"b,-j @= & )& @ ++ "0 2" ,!% ,# ,!% !"#" ##& 5& 0" #!" # ! 2 ## # #% ++ k*#& $" # ! "# e@ ++. & g& j @= <j ++ s&*j j @; o1&j& 6& " !!" "# #!j ++ j ++ #& 8& j ++ <j == ++"& :& ""# ! "# 0 "!" *:f*8c& + ""# ! "# "!"$ *:f*5gc& " , #>2 ," < 1 $ $ $ ! 0 $/ j0 0 !! 0 !! j0 !! + ]@ s# $ 1 1 ' ! 8 0 1k j0 0 !! 0 !! j0 !! + ]@ s# $ !!a 0 !! # : ! !-lj0 $ 1-lj0 $2 .-lj0 $2 j> 7;42& 86 7; # ==42& 8> =? # >?42& f? == # !-lj0 $ 1-lj0 $2 .-lj0 $2 j@= 7;42& 8> ;> # ==42& f? 7; # >?42& f8 =? # !-lj0 $ 1-lj0 $2 .-lj0 $2 jf8 7;42& 89 ;8 # ==42& f8 ;> # >?42& f; 7; # !-lj0 $ 1-lj0 $2 .-lj0 $2 j! 7;42& f8 f= # ==42& f7 ;8 # >?42& f> ;> # $ !!@ 0 !! # # : ! f !-lj0 $ 1-lj0 $2 .-lj0 $2 @?42& f; ;7 # 742& @6 8= # @42& ; 6 # $ !!8 0 !! # . ! ; !-lj0 $ 1-lj0 $2 #!!j0 $2 0 #!! @7s# 0 !! 8; 787 # $ !!f 0 !! ! 7 = !-lj:--lj 0 !! ]?80 0 #!! @7s# 0 !! 8? 6? s# $ !!; 0 !! : ! = :--lj0 $ ! mj0 $ 6? 87? s# $ !!7 0 !! # ! : . . = !-lj0 $ 1-lj0 $2 #!!j0 $2 i 742& 7? =? # $ !!= 0 !! ! = !-lj0 $ 1-lj0 $2 86?s# $ #!! # ! 6 !-lj0 $ 1-lj0 $2 0 #!! j970 0 #!! =8? # 0 !! @; 8? # 0 $ $ "0 0 !! j@>0 c?7 ?; 0 0 $2 $ 20 0 !! j@>0 0 !! c?; 0 !! e?; 0 0 1 1 "0 $ 1 j@??s# 0 !! j0 !! j0 !! ?@ 0 0 12 1 20 $ 12 jc@??s# 0 !! j0 !! j0 !! 0 !! 0 0 22 0 # >7 97 0 0 m1 "0 !! '% 0 @; 0 september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 66 advance information/preliminary 14.8 ac characteristics #@$2$# d?* 8 & ""# ! "# 0 "!" *:f*8c& + ""# ! "# "!"$ *:f*5gc& *& ct # & figure 14.6. clk characterization parameter description 54 mhz 66 mhz 80 mhz unit ! m ! m, 4+ 7; == >? 42& ! m ! m 4 @>7 @7@ @87 !2 ! m2 4 6; =@ 7? ! ! m " !: ! m: 4+ f f 87 !, ! m, t clk t cl t ch t cr t cf clk 67 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary #@$2$: -* 3/ & ## # "#"#" +;9& *& ct # & .& ""# ! "# 0 "!" *:f*8c& + ""# ! "# "!"$ *:f*5gc& parameter description 54 mhz 66 mhz 80 mhz unit jedec standard $#!! 4+ >? a#!! a # 0! '1 4+ @f7 @@8 9 #! # ! m/ @ 4 7 ; #!2 # 2 ! m/ @ 4 6 = a 2 2 / +! '! 4 ; f !: !- : n0 4+ @f7 @@8 9 1- 1 - 1 0 4+ @f7 @@8 !-w !- 2w/ 8 4+ @? 1-w 1 - 2w/ 8 4+ @? !- !-l ! m 4 ; : n : n ! m 4 7 ; f7 :#!! : # ! m 4+ @f7 @@8 9 !# !-l #0 l 4 ? #0! #0 l "! m 4 ; #0 #0 l 4 > ! m 4 ' 4 @@@42& table 14.2 synchronous wait state requirements < g 7 - g ?@42&^, @;42& 8 @;42&^, 8642& f 8642&^, ;?42& ; ;?42&^, 7;42& 7 7;42&^, =642& = =642&^, >?42& 6 september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 68 advance information/preliminary #@$2$9 , & /" #2#!% 2"# ## "0 $ #& !% 2"# # % !! !2 $ ## 0 $ #& *& @$%# ## #l ##k m l ##k*m l ##k.m "" $ $ # "# " " %$(r& .& 0" "#"#$ #! & figure 14.7. clk synchronous burst mode read da da + 1 da + n oe# data (n) addresses aa avd# rdy (n) clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 5 cycles for initial access shown. 18.5 ns typ. (54 mhz) hi-z hi-z hi-z 12 3456 7 t rdys t bacc da + 3 da + 2 da da + 1 da + n data (n + 1) rdy (n + 1) hi-z hi-z hi-z da + 2 da + 2 da da + 1 da + n data (n + 2) rdy (n + 2) hi-z hi-z hi-z da + 1 da + 1 da da da + n data (n + 3) rdy (n + 3) hi-z hi-z hi-z da da t cr 69 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary & /" #2#!% 2"# ## # 0 $ #& !% 2"# # % !! !2 $ ## 0 $ #& *& @$%# ## #l ##km l ##k*m l ##k.m "" $ $ # "# " " %$(r& .& 0" "#"#$ #! 2"2 & )& 81/" 20 !" " 2"" "0 832 ## !2 #" #&" ##"" "# ) ##" 3/ & figure 14.8. 8-word linear burst with wrap around & /" #2#!% 2"# ## # 0 $ #& !% 2"# # % !! !2 $ ## 0 $ #&+ "## "0 "#" & *& @$%# ## #l ##km l ##k*m l ##k.m "" $ $ # "# " " %$(r& .& 0" "#"#$ #! 2"2 & )& +1." 20 !" " 2"" "0 832 ## !2 #" #&" ##"" "# # ##" 3. & figure 14.9. 8-word linear burst without wrap around dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df db 7 cycles for initial access shown. hi-z t racc 1234567 t rdys t bacc t cr d8 t racc dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df db 7 cycles for initial access shown. hi-z t racc 1234567 t rdys t bacc t cr d8 t racc september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 70 advance information/preliminary & /" ##! #g2"# #""" ## #$ # & *& +" "( "# !! # e #% 2" 2"+(8<d 0" #(r $ % 0" & figure 14.10. linear burst with rdy set one cycle before data #@$2$@ * l * & ct # & *& ""# ! "# 0 "!" *:f*8c& parameter description 54 mhz 66 mhz 80 mhz unit jedec standard !- # !-l " 4+ >? #!! # # 4+ >? #0 #0 l " 4 > ##0 # : - #0 l 4 ; ##0 2 # 2 : - #0 l 4 6 = 1- 1 - 1 0 4+ @f7 1-2 1 - 2 : 4 ? l 4 @? 1-w 1 - 2w / 4+ @? !# !-l #0 l 4 ? da+1 da da+2 da+3 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 6 wait cycles for initial access shown. hi-z hi-z hi-z 1567 t rdys t bacc t cr ~ ~ ~ ~ ~ ~ ~ ~ 71 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary ( <( ## (<( & figure 14.11. asynchronous mode read t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez t aavdh t avdp t aavds avd# ra t cas september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 72 advance information/preliminary #@$2$( ) ! a-a,c & ct # & *& ""# ! "# 0 "!" *:f*8c&+ ""# ! "# "!"$ *:f*5gc& figure 14.12. reset timings parameter description all speed options unit jedec std. : :--l . 4 f? s :2 : 2 a : / 4 8?? reset# t rp ce#, oe# t rh 73 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary #@$2$= a 3 , & ct # & *& #$ # ! 2# #$ # ! " $&$ # ! 2#% #$ # $ # ! "& .& @#$ # ! ""!" ## # " f,-&@# $ # ! " "!" ## # "#" +;9& )& l,# !!" ! m # "! "!"& 5& #" !!" "! & g& ""# ! "# 0 "!" *:f*8c&+ ""# ! "# "!"$ *:f*5 gc& parameter description 54 mhz 66 mhz 80 mhz unit jedec standard #0#0 .! . ! / @ 4 >? #0. # # / 8 f 4 7 # ? . #t #2 # 2 / 8 f 4 9 # 8? #0 #0 l " 4 > 0.2 4 ;7 8? .2 t 2 2 4 ? b2. b2. : : a . 4 ? !# !-l #0 l 4 ? .2-2 !2 !-l2 4 ? . .2 . . . 4 f? .2. .2 . .2 4 8? :g. a " : . 1 4 ? 0$ 0 #!! : , 4 7?? 0$ 0 #!! # 4 @ s - . ! !-l .-l 4 7 #0. #0 l .-l 4 7 #02. #0 l2 .-l 4 7 #0! #0 l ! m 4 7 #02! #0 l2 ! m 4 7 !. ! ' .-l 4 7 .- / 4 .-l 4+ f -# - # % 4+ 7? s - - 4+ 8? s 4+ 8? s # - " ? s . ? s september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 74 advance information/preliminary figure 14.13. chip/sector erase operation timings oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h 75 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary & < ! ## < ! j <j" ## " ##%"#& *& l@ ##m l ! m ## ! "& .& *.1 ) f*5gc **1 ) f*8c ? " !! # e $ #& )& +;9 % " j @; j @= & 5& #$ # !!" ""#" 0" ( ' %"" +" "( "# & figure 14.14. program operation timing using avd# oe# ce# data addresses avd# we# clk v cc 555h pd t as t avsw t avhw t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs t cas september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 76 advance information/preliminary & < ! ## < ! j <j" ## " ##%"#& *& l@ ##m l ! m ## ! "& .& *.1 ) f*5gc **1 ) f*8c ? " !! # e $ #& )& ## # "#"#" +;9& 5& ," +,- j-"# e" !2" "% 2 !!" !! # e #& g& $ # !!" ""# 0" ( ' %"" +" " ( "# & +" "( "# ! #% # $ #( ' & figure 14.15. program operation timing using clk in relationship to avd# oe# ce# data addresses we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t cas t ah t avch t csw t avsc avd# 77 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary # # "! #! 0 " ! "& figure 14.16. accelerated unlock bypass programming timing & # #"" #2##$ #& *& j <j" ##&2 $ # e" !" ##&f ,!% "! ""# ! - " # & figure 14.17. data# polling timings (during embedded algorithm) ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id v il or v ih t vid t vids we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 78 advance information/preliminary & # #"" #2##$ #& *& j <j" ##&2 $ # e" !" ##&f ,!% "! ""# ! %"# # " & figure 14.18. toggle bit timings (during embedded algorithm) & "!" # #"!"#$ # "!" #& *& j <j" ##&2 $ # e" !" ##&f ,!% "! ""# ! %"# # " & .& (r"# "0 2" 8<" +" "( "# &f 8<" +" "( "# (r"# "0 $ % & figure 14.19. synchronous data polling timings/toggle bit timings we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc 79 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary & (r "0 2" 8< " +" "( "# & *& (r* "0 $ % 8<" +" "( "# & .& +44" " # " #44 #d 4! +g" #g& )& /" #2# 0" ##" % " ## !" # !& 5& (r # 2 "" 2"# # e" f 5& figure 14.21. latency with boundary crossing when frequency > 66 mhz enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing h* #$2 ##2"" # 3## # & #$# !!$# b,-+,- h* hg& figure 14.20. dq2 vs. dq6 clk address (hex) c124 c125 c126 c127 c127 c128 c129 c130 c131 d124 d125 d126 d127 d128 d129 d130 (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f 80 81 82 83 latency rdy(2) latency t racc t racc t racc t racc september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 80 advance information/preliminary & (r "0 2" 8< " +" "( "# & *& (r* "0 $ % 8<" +" "( "# & .& +44" " # " #44 #d 4! +g" #g& )& /" #2# 0" ##" % " ## !" # !& 5& (r # 2 "" 2"# # e" f 5& figure 14.22. latency with boundary crossing into program/erase bank clk address (hex) c124 c125 c126 c127 c127 d124 d125 d126 d127 read status (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f latency rdy(2) latency t racc t racc t racc t racc 81 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary ) & 2* ' &'3 . * <lm ? ( # 0 . * <lm ? ( # 0 . * <lm ? 5 !! 6 . * <lm ? ) !! g . * <lm ? . !! 5 /" ##! # ##"# ##% $ 2"# "## lm& figure 14.23. example of wait states insertion data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45 september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 82 advance information/preliminary "#"20 !#" " #$# !!$ $ $ ! l3%#$% m2" " ## ! # "" l%#$m% & #$# !# ##2" # 0" "!"& figure 14.24. back-to-back read/write cycle timings oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t ds t dh t oe t as t ah t acc t oeh t wp t ghwl t oez t write cycle t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph t write cycle t read cycle t read cycle 83 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary #@$2$% a & $" ! # "! ###! 2" ""#n*5 + &8jj ++ $ #d % & *& 2# # ""#:u+ j ++ <&6j $ #& .& $" " !! " "! "# #" %$ ## !4"!! " !!" "! "# "#%# ""7" f" & )& @ 3 !!" # ,!% ,# "! 2 # !! % # & 5& $# !3 0 0 "# "! e" 4 233%#3 $ # e ! !! & "4 "!" !! """#& g& + # #" !""!! $ " 0 #" # "" " "# " ""#& 6& ( " "c l,# # a( #! "!" m! "#& 8& f !!" # "" ""#%# #" 2 !!" " ""7" 2" % & :& ""# ! "# 0 " !" *:f*8c&+ ""# ! "# "!"$ *:f*5gc& parameter typ (note 1) max (note 2) unit comments - =;m" 0 !! ?= f7 -+ ?? / ; @=m" 0 !! ^?@7 8 !- 0 !! @7f=.87=/ 66;.@8>/ f?>.87=/ @7;.@8>/ #!! @f?=.87=/ =7>.@8>/ 8=8.87=/ @f8.@8>/ . / > 0 !! ;? ;?? s #!! 8; 8;? - . & . a 0 !! 9; 9; s #!! = =? f8%.a 0 !! f?? f??? s #!! @98 @98? ! / f 0 !! @76f.87=/ 6>=.@8>/ f@;=.87=/ @76f.@8>/ -+ / 7 #!! @??6.87=/ 7?f.@8>/ 8?@f.87=/ @??6.@8>/ september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 84 advance information/preliminary #@$2$2 /j/ " & ! t # & *& # ""# <*5 +d<&'=7& .& ""# ! "# 0 "!" *:f*8c& + ""# ! "# "!"$ *:f*5gc& parameter symbol parameter description test setup typ. max unit ! $/ $ ! 0 $/ j? 7f =f , ! 1k 1 ! 0 1k j? 7> => , ! $/8 ! ! 0 $/ j? =f 6f , 85 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary 15 appendix " " , , " # : % @6 + . """ """ 5 september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 86 advance information/preliminary table 15.1 memory array commands -g / #5( - ,* * * -<* # : = @ :# : : 6 @ ttt ,? # % > 4 $ ; 777 ## 8## 77 xa#y777 9? xa#yt?? ???@ $ 9 = 777 ## 8## 77 xa#y777 9? xa#yt?@ 886- a#et?- a#et?, 88?? $ a @? ; 777 ## 8## 77 xa#y777 9? xa#yt?f ; 777 ## 8## 77 777 #? # . a @@ = 777 ## 8## 77 # 87 # .! # .a a , @ # 89 . a #: @8 f 777 ## 8## 77 777 ,? !- = 777 ## 8## 77 777 >? 777 ## 8## 77 777 @? - = 777 ## 8## 77 777 >? 777 ## 8## 77 # f? - g @f @ a# a? - g : @; @a#f? ! : @> ; 777 ## 8## 77 777 ? t?? !: : ! : ; 777 ## 8## 77 777 != t?? !: !,$3 @7 @ xa#y777 9> k 'a 4 - f 777 ## 8## 77 777 8? @= 8 ttt #? # !,$ @= @ ttt 9> : 8 ttt 9? ttt ?? - f 777 ## 8## 77 777 >> @6 ; 777 ## 8## 77 777 #? # : @6 @ ?? -+ @6 ; 777 ## 8## 77 777 9? ttt ?? ><? & ( <( ##& (<( & < ! ##& ## # "#" j-# "0 +;9 2" 0 #"#& < !& # "#" f,-+,- # 2" 0 #"#& < ##&f*5gc< *.1 )df*8c< **1 )& < ##&f*5gc< *.1 *df*8c< **1 *& +(<+" "( "# %"#51& f ;<f" ; "& ##!#% 2"" #! 2" % # & f+<f +&c!% 2" % "# !"#& & % & # ""%# "#& *& 0 # " 4 "!& .& #" " $ #& )& ## %"## "" "% # ? # 4 " ""!" #)%"# & 5& f"" " ## 0 #2"" !" "! # e !$ 0" " 2# & #$# !!#2" # !! 0" " $ & g& c !! $ # e" 2 % "# " $ & 6& ( # !! "# e" " $ # 3## 3 ! " 0"#$",# # 2 % "#" # ! "h5 #" 2" % "#0" " ##"!" !" # a & 8& #$# !!#0" % ##& # # "! "!" :& " $ 5"#**.f*5gc **.f*8c & & % &: " " %"0 #& & !% $ #" !! # e "# !" %$ !% 2 #2" 2" % & *& +!! # e # # 0" 4 !! 2" 3 3% "& .& $# !!$ !"3 #" # # # ! 2 " ,# # ! & ,# # !! "#0" $ " # # " e" # % ##& )& ,# ( #! !! "#0" $ " ,# # ! e" # % ##& 5& +!! "#0" 2 0" "# $ $ 2 0" "#"# ! & ## e#55 0" # %555f*5gca*8c& g& ( e" #,$ !! # e " 4 "& $##( # !! "# e" " $ & 6& ( e" #,$ !! # e " 4 "& "" ,4"( # !! "# e" 4""#! d 0" !$ 2"# % " 2# & 8& ( e" # # !! " +" "( "# & 87 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary table 15.2. sector protection commands -g / #5@ - ,* * * -<* -* ' : a ! - 7 f 777 ## 8## 77 777 ;? = @8 8 tt #? 66g?? : = @ 66 ! -+6 8 tt 9? tt ?? " ! - 7 f 777 ## 8## 77 777 =? x?%fy> 8 tt #? ?? . x?%fy : 9 ; ??? . ? ??@ . @ ??8 . 8 ??f . f k ' 6 ?? 87 ?? ?f ?? . ? ?@ . @ ?8 . 8 ?f . f ?? 89 ! -+6 8 tt 9? tt ?? / %0 a ! - 7 f 777 ## 8## 77 xa#y777 !? a @? 8 tt #? # ?? #a- @? @@ 8 tt >? ?? f? a : @ # : ? ! -+6 8 tt 9? tt ?? b 0 , & a ' ! - 7 f 777 ## 8## 77 xa#y777 7? a 'a 8 tt #? tt ?? a 'a : @ a# : ? ! -+6 8 tt 9? tt ?? 0 na ! - 7 f 777 ## 8## 77 xa#y777 -? na 8 tt #? # ?? na! 8 tt #? # ?@ na : @ # : ? ! -+6 8 tt 9? tt ?? ><? & ( < ## ! !$ "% & < "" ; "& %"& < #"# "' ; "& %" !# % # i? "2" * %"*!#% #i?& * <##2 "' ; "&* %"* !# % # i? "2" %"!#% #i?& . < "' b "&. %".& < ##&f*5gc < *.1 )df*8c< **1 )& < ##&f*5gc< *.1 *df*8c< **1 *& f.1f<##2 &.1 # g%" !%""# # g)3%"##2 f <##2 ##& ##%"# # # g3%"" g)3%" "$& f<##2 & ( ( (* <h h h* "" " %"&@ h h h*<&@ h h h*<& & 0 # " 4 "!& *& #" " $ #& .& ## %"## "" "% # ? # 4 " ""!" #)%"# & )& f"" " ## 0 #2"" !" "! # e !$ 0" " 2# & #$# !!#2" # !! 0" " $ & 5& ,$ !! # e" # "" ! % "# "#$0"% 2""! & g& @% #"# "' ; " " ##2 "' ; " " # #! "! !! "%# # 0" #"# "' " * %# $ & c 0" # ## # e %"# $66 f*5gc$& % # & &* 4" %"#& 6& ,4" !! !#% "## # 0" " ! d 0" !$ 2"# % " 2# & 8& ," 2%#3 $ # e ! #% " ##2 & :& / ## "# e" " ##2 & & /" &* "#& & l ,# m !! 3 !# #% # 0 0 3 # & *& # $ ## "# ! " "#66*:f*5gcd2 0 f*8c"# ##"#& september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 88 advance information/preliminary 15.1 common flash memory interface ! ,$ !,$ " % ' " " % %" " % p- -!$ % % "% '%"% , & + % !,$3 " " !,$3 9> a#777 !,$ @7fc@7= " '# !,$ " ' % : ' % " " !,$ " " ! + !,$- -+ : #";2; 0 "0 # ?# " """ """ 5 , " /* example: cfi entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00f0; /* write cfi exit command */ , !,$ p- -! p-@f6%# p- =>?@ !,$ @?? table 15.3. cfi query identification string addresses data description @? @@ @8 ??7@ ??78 ??79 3 k #!$$ )3:n* @f @; ???8 ???? 1-4! @7 @= ??;? ???? # -+ @6 @> ???? ???? # 1-4! ??j + @9 @# ???? ???? # # 1-4-+ ??j + table 15.4. system interface string addresses data description @a ??@6 0 !! 4 " g 6c ;( fc ?(@?? @! ??@9 0 !! 4+" g 6c ;( fc ?(@?? @ ???? 0 4 ??j 0 @- ???? 0 4+ ??j 0 @, ???= g"" 8 s 8? ???9 4 & " 8 s??j 8@ ???# ' 8 88 ???? 8 ??j 8f ???; 4+ g"" 8 8; ???; 4+ " 8 87 ???f 4+ ' 8 8= ???? 4+ 8 ??j 89 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary table 15.5. device geometry definition addresses data description 86 ??@9.87=/ ??@>.@8>/ & j8 8> 89 ???@ ???? , $ !,$ @?? 8# 8a ???= ???? 4+ % " j8 ??j 8! ???f / - a ': " 8 8- 8, f? ???f ???? ??>? ???? - a ': @$ !,$ !,$ @?? f@ ??, .87=/ ??6 .@8>/ - a ': 8$ f8 ff f; ???? ???? ???8 f7 f= f6 f> ???f ???? ??>? ???? - a ': f$ f9 f# fa f! ???? ???? ???? ???? - a ': ;$ september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 90 advance information/preliminary table 15.6. primary vendor-specific extended query addresses data description ;? ;@ ;8 ??7? ??78 ??;9 3 % #!$$ ):$* ;f ??f@ 45 #!$$ ;; ??f; 4 #!$$ ;7 ?@?? # k 'a@%? ?j: @j/: a7%8?@??j?@@s ;= ???8 - ?j/ @j: 1 8j: h. ;6 ???@ ?j/ tj/ ;> ???? k ??j/ ?@j ;9 ???> gk ?>j# ;# ??,f.87=/ ??6a.@8>/ 1 / ' + ' ;a ???@ a 4 ??j/ ?@j ;! ???? 4 ??j/ ?@j;. ?8j>. ?;j@=. ; ??>7 #!!# 4 ??j/ 6% ;(0 f% ?(@?? 0 ;- ??97 #!!# 4+ ??j/ 6% ;(0 f% ?(@?? 0 ;, ???@ ga a , ???@j a 7? ???@ ??j 7@ ???@ k 'a ??j/ ?@j 78 ???6 ! 1# & 8 7f ??@; 2" : " % 4+ 8 7; ??@; 2" : " % 4+ 8 77 ???7 - % 4+ 8 7= ???7 % 4+ 8 76 ??@? a '1 & (tj/ ' 7> ??@f.87=/ ???a.@8>/ a '?: $ tj/ ' 79 ??@?.87=/ ???>.@8>/ a '@: $ tj/ ' 91 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information/preliminary 7# ??@?.87=/ ???>.@8>/ a '8: $ tj/ ' 7a ??@?.87=/ ???>.@8>/ a 'f: $ tj/ ' 7! ??@?.87=/ ???>.@8>/ a ';: $ tj/ ' 7 ??@?.87=/ ???>.@8>/ a '7: $ tj/ ' 7- ??@?.87=/ ???>.@8>/ a '=: $ tj/ ' 7, ??@?.87=/ ???>.@8>/ a '6: $ tj/ ' =? ??@?.87=/ ???>.@8>/ a '>: $ tj/ ' =@ ??@?.87=/ ???>.@8>/ a '9: $ tj/ ' =8 ??@?.87=/ ???>.@8>/ a '@?: $ tj/ ' =f ??@?.87=/ ???>.@8>/ a '@@: $ tj/ ' =; ??@?.87=/ ???>.@8>/ a '@8: $ tj/ ' =7 ??@?.87=/ ???>.@8>/ a '@f: $ tj/ ' == ??@?.87=/ ???>.@8>/ a '@;: $ tj/ ' =6 ??@f.87=/ ???a.@8>/ a '@7: $ tj/ ' table 15.6. primary vendor-specific extended query (continued) addresses data description september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 92 advance information 16 commonly used terms te r m d e f i n i t i o n #!! #!! # " " " 0 !! $ #!! " " # + 4 x#8f87=4 #88@8>4 #8@ =;4y # #? # 1 " ' # : " a ' # ' ' " a & , & " " % a a : #$ # a > !,$ ! ,$ #, xp- -!@f6% # p- =>?@y " , & ! w " ! : " ! : " " " " - : , 1 2 - g- : 2 " ab# ab# ' ! " (, ab# , % ab# ' " : " > @= f8" " " " " $ 4! 4 %! ' # ' # " 4 # 4av v ' 93 s75ws-n based mcps s75ws-n_02_a1 september 8, 2005 advance information b " "" : # " " " ' " ' " " " " , $ , @80 , # 7 # g : 2 : 2 , : ' # 87= " " $ 1 " " k " $ # # " 1 4 " ' " " " ' : ' + 1 1 " ' " ' " ' 0 $1v0 $1 " " k 'a 4 " $ "k ' 2" ; c " " . " @= # "" " "" # " " " te r m d e f i n i t i o n september 8, 2005 s75ws-n_02_a1 s75ws-n based mcps 94 advance information . " 2# ' " " a . ;" ?f "8" " 8 f ? @ . $ g " " " 2"" !! $ # + . a 4 %" " " $ # . a @=f8" @=f8" . a 4 " " + & . a k . a > " . 1 #" $ te r m d e f i n i t i o n publication number s75ws_02 revision a amendment 1 issue date september 8, 2005 preliminary 1.8v psram type 4 8m x 16-bit synchronous burst psram features (!41 1 & (>4+@= " 0 (@6_8?0 1 4:4 : 4: %4: ! " % #: $ !: 1 & " # ;% : # . 1 a : # . 1 # "# 0 a : a . 1 a : g. 1 < ;"g>" g@=" , 87=" < a h$ a < ( 7i==42&! @? ;i7;42&! @? < a : /! ' < a . 4 ' gkahg a < .#$ 4+a ! ', (==42& september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 96 preliminary 17 pin description 18 power up sequence # 0 !! @60 !l 4:l " .8 ??s % " " " " @ #" 8 4 " 0 !! j@60 8? ?s"!l 4:l pin name function type description ! m ! ' $ ! ! m # 0l # 0 0# # 0 4:l 4 : 4:l" 4 : !l ! !l" !l 1-l 1 - 1-l" .-l . - .-l" " al " a $g1 ?_6 kal al" " kal k a $g1 >_@7 #?%#88 # ?_# 88 0 " # 0" 4 " 4:" $g1?%$g1@7 $ g1 $ g1 kal al "@=% kal al" >% kal "h al" >% al" kal 0 !! 0 " ! " 0 !!3 0 " $g1" 0 b b/ ! 0 3 $g1b b/ $g1b .#$l 0 $ 1 .#$l " 97 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 19 power up and standby mode timing diagrams 19.1 power up j ++ #j ++ '"& 2"*p#2"+- '(-" &"## 0" "! "& figure 19.1 power up timing 19.2 standby mode figure 19.2 standby mode state machines " # ; : # . a @??` 4:l % " , #: 4:l 0 $ ?7s 4:l #;j@ #fj?$ 4:l 0 $2 #: " "' _ _ v cc v cc(min) min. mrs# cs# min. 0ns power up mode min. 0ns normal operation 200 s 200 s _ _ _ _ active standby mode par mode mrs setting cs# = v ih mrs# = v ih cs# = ub# = lb# = v il we# = v il , mrs# = v ih cs# = v il , ub# or lb# = v il mrs# = v ih cs# = v ih mrs# = v ih mrs# = v il cs# = v il we# = v il , mrs#=v il mrs setting initial state (wait 200 s) power on september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 98 preliminary 20 functional description table 20.1 asynchronous 4 page read & asynchronous write mode (a15/a14=0/0) ><? !#% 2" # & & @#$ #! + j- " & *& f @-""#=" 3v"#$ #! & ta b l e 2 0 . 2 synchronous burst read & asynchronous write mode (a15/a14=0/1) & >!#% 2" # & *& >! #l? m % 2 " " & .& f @-"# 0" #" #0 $ ! """& # "!" " !f"-" "& mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 power 2 2 t t t t 2%w 2%w 2 t t t t 2%w 2%w #: 1 2 2 2 t t 2%w 2%w # 1 2 t t 2 2 2%w 2%w # " a : 2 2 2 1k 2%w # k a : 2 2 2 2%w 1k # .: 2 2 1k 1k # " a . 2 2 2 $/ 2%w # k a . 2 2 2 2%w $/ # .. 2 2 $/ $/ # 4 : 2 2%w 2%w # mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 clk adv# power 2 2 t t t t 2%w 2%w t 8 t 8 2 t t t t 2%w 2%w t 8 t 8 #: 1 2 2 2 t t 2%w 2%w t 8 2# 1 2 t t 2 2 2%w 2%w t 8 2# : ! 2 t 2 t t 2%w 2%w # " a : 2 2 2 1k 2%w 2 # k a : 2 2 2 2%w 1k 2# .: 2 2 1k 1k 2# " a . 2 2 2 $/ 2%w t 8 # k a . 2 2 2 2%w $/ t 8 # .. 2 2 $/ $/ t 8 # 4 : 2 2%w 2%w t 8 # 99 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary ta b l e 2 0 . 3 synchronous burst read & synchronous burst write mode(a15/a14 = 1/0) & >!#% 2" # & *& >! #l? m % 2 " " & .& f @-"# 0" #" #0 $ ! """& # "!" " !f @-" "& mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 clk adv# power 2 2 t @ t @ t @ t @ 2%w 2%w t 8 t 8 2 t @ t @ t @ t @ 2%w 2%w t 8 t 8 #: 1 2 2 2 t t 2%w 2%w t 8 2# 1 2 t @ t @ 2 2 2%w 2%w t 8 2# : ! 2 t @ 2 t t 2%w 2%w # " a : 2 2 2 1k 2%w 2 # k a : 2 2 2 2%w 1k 2# .: 2 2 1k 1k 2# . ! 2 t @ 2%w 2%w # " a . 22 t @ 2 $/ 2%w 2 # k a . 22 t @ 2 2%w $/ 2# .. 2 2 t @ $/ $/ 2# 4 : 2 2%w 2%w # september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 100 preliminary 21 mode register setting operation ( # : # . a : a . #: #: #: #: 4 : 4: 4: " g" 21.1 mode regist er set (mrs) :#4$ #: #: ' :#4 " " !l # 0l .-l kal al 4:l0 $ 1-l0 $2 #: #?_#; a #7_#6 a #> ! #9_#@@ . #@f 1 4 #@;_#@7 #@=_#@6 : " 4 : #@>_#88 ) r * 4 : table 21.1 mode register setting according to field of function "0 '' ff""$ ; $; $+ #$ ; # ; (" $( # ( " $( # $ ( " $( #"7 (/( # 0 / # & ta b l e 2 1 . 2 mode register set address a17 C a16 a15 C a14 a13 a12 a11 C a19 a8 a7 C a5 a4 C a3 a2 a1 C a0 function 4 . :,k a a #: #:# #: driver strength mode select a17 a16 ds a15 a14 ms ? ? , @ ? ? # ; : g# . @ ? @ @g8 ? @ a : g# . @ ? @g; @ ? a : g a . wait# polarity rfu latency count burst type burst length a13 wp a12 rfu a11 a10 a9 latency a8 bt a7 a6 a5 bl ? "- @ ? 4 @ ? ? ? f ? @ ? @ ? ;" @ 2- @ < ? ? @ ; @ $ ? @ @ >" ? @ ? 7 @ ? ? @=" @ ? @ @ = @ @ @ , 87=" 101 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary ! & ##%"# # "# " % %0 # 0 &/ 4! #; ##%"# 6n gn 5 0 )# # # 0 %"#" nn nn nn nn&@ # 0 ##%"# " ! 2"% # ! &, " #"#2 ! %"# ! "#t 3 # '(# " # e "#" $ !! 2 & *"# # 0 %" # & *!# % # #lm&c ! # " # # & ! # " #% # # #"& *5g 2 / %#! #! + #+$ "! ! #!4&*5#& 21.2 mrs pin control type mode register setting timing $ 4: " 1 + #: 4 : 4:l 0 $ % " ?7s " !l # 0l kal al .-l0 $ 1-l0 $2 $ " .-l " ?7s #: figure 21.1 mode register setting timing (oe# = v ih ) ta b l e 2 1 . 3 mrs ac characteristics j ++ <&6w*&j <3)85u+ '4"!!'"+ / e $ september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 102 preliminary 22 asynchronous operation 22.1 asynchronous 4 page read operation # " !l 1-l kal al 0 $ " #? #@$ #? #@ " " :! " " ! 4:l .-l 0 $2 ! ' # 0l .#$l 22.2 asynchronous write operation # " " !l .-l kal al 0 $ 4:l 1-l 0 $2 " ! ' # 0l .#$l 22.3 asynchronous write oper ation in synchronous mode #" " !l .-l kal al 0 $ % ! ' " 4:l 1-l 0 $2 " # 0l 0 $ ! ' # 0l .#$l figure 22.1 asynchronous 4-page read figure 22.2 asynchronous write a1~a0 cs# oe# a22~a2 ub#, lb# data out high-z high- z high-z address cs# we# data in data out ub#, lb# 103 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 23 synchronous burst operation a " '# 0l" !l ' .-l " : .-l2. .-l " , & a 4 " ' % ! " " a " a ( $ . 8 @ 8 23.1 synchronous burst read operation a : " ' # 0l" # 0l !l ' : .-l 0 $2 ' "# 0l " ' " " ! 23.2 synchronous burst write operation a . " ' # 0l .-l" # 0l .-l !l ' ' "# 0l " ' " " '" ; $5 ;) fn;2,% figure 23.1 synchronous burst read ; $5 ;) fn;2,% figure 23.2 synchronous burst write clk adv# addr. oe# cs# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ub#, lb# wait# data out clk adv# addr . we# cs# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 wait# data in ub#, lb# september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 104 preliminary 24 synchronous burst operation terminology 24.1 clock (clk) ' " :#4 " & ' ' " " 0 $ 0 $2 24.2 latency count ! " ' ' 8 ; @ " ! table 24.1 latency count support ta b l e 2 4 . 2 number of cloc ks for 1st data "# 2"2$# ; $&/! # #! " 2""! !$% # %$ f @-"& figure 24.1 latency configuration (read) 24.3 burst length a " ;" >" @=" 87=" " 87=", a! a ! 87?? + " " e ! , " " ! ' clock frequency up to 66 mhz up to 54 mhz up to 40 mhz latency count 7;f set latency latency 3 latency 4 latency 5 # of clocks for 1st data (read) ;7= # of clocks for 1st data (write) 8f; address data out adv# clock dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 data out dq1 dq2 dq3 dq4 dq5 dq6 latency 3 latency 4 latency 5 latency 6 t 105 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 24.4 burst stop a " " $ !l 0 $2 % " " & % @ 8 24.5 wait control (wait#) .#$l r " r% % " , .#$l . " , .#$l .#$l ' : . ; ,c+rn5 #; n) fn;2,% figure 24.2 wait# and read/write latency control 12345678910111213 adv# read clk dq0 dq1 0 dq2 write d0 d1 d2 dq3 d3 data out data in cs# latency 5 latency 5 high-z wait# high-z wait# september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 106 preliminary 24.6 burst type $ $ " 8 ; f ta b l e 2 4 . 3 burst sequence start address burst address sequence (decimal) wrap (note 1) 4 word burst 8 word burst 16 word burst full page(256 word) linear interleave linear interleave linear interleave linear ? ?%@%8%f ?%@%8%f ?%@%%7%=%6 ?%@%8%%=%6 ?%@%8%%@;%@7 ?%@%8%f%;@;%@7 ?%@%8%%87;%877 @ @%8%f%? @%?%f%8 @%8%%=%6%? @%?%f%%6%= @%8%f%%@7%? @%?%f%8%7@7%@; @%8%f%%877%? 8 8%f%?%@ 8%f%?%@ 8%f%%6%?%@ 8%f%?%%;%7 8%f%;%%?%@ 8%f%?%@%=@8%@f 8%f%;%%877%?%@ f f%?%@%8 f%8%@%? f%;%%?%@%8 f%8%@%%7%; f%;%7%%@%8 f%8%@%?%6@f%@8 f%;%7%%877%?%@%8 ; ;%7%%@%8%f ;%7%=%%8%f ;%7%=%%8%f ;%7%=%6%?@?%@@ ;%7%=%%877%?%@%8%f 7 7%=%%8%f%; 7%;%6%%f%8 7%=%6%%f%; 7%;%6%=%@@@%@? 7%=%6%%877%%f%; = =%6%%f%;%7 =%6%;%%?%@ =%6%>%%;%7 =%6%;%7%8>%9 =%6%>%%877%%;%7 6 6%?%%;%7%= 6%=%7%%@%? 6%>%9%%7%= 6%=%7%;%f9%> 6%>%9%%877%%7%= ____ @; @;%@7%?%%@8%@f @;%@7%@8%%?%@ @;%@7%%877%%@8%@f @7 @7%?%@%%@f%@; @7%@;%@f%%@%? @7%@=%%877%%@f%@; _ _ 877 877%?%@%%87f%87; 107 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 25 low power features 25.1 internal tcsr ! : !: % ";?d! :#4 " ' 2 " . !: " >7d! a " !: " ;?d! & ";?d! figure 25.1 par mode execution and exit table 25.1 par mode characteristics & b$ " # % 0" & *& ( $ % # ' ( "# # ' ( "# " b " & 25.2 driver strength optimization & 5 & & @g8 @g; 25.3 partial array refresh (par) mode #: & :#4 ; ' @ ' 8 ' f ' ' 4 : " - #: 4 : #: + 4:l + % 4:l " ?7s 4:l 2 ' #: + : , 87@ 8 7 @ #: #: power mode address (bottom array) (note 2) address (top array) (note 2) memory cell data standby current (a, max) wait time (s) , # ??????_6,,,,, ??????_6,,,,, 0 @ 8?? ? : fg;a ' ??????_7,,,,, 8?????_6,,,,, @6? : @g8a ' ??????_f,,,,, ;?????_6,,,,, @7? : @g;a ' ??????_@,,,,, =?????_6,,,,, @;? mrs# mode cs# normal operation 0.5 s suspend par mode normal operation september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 108 preliminary 26 absolute maximum ratings ## # # "# %# '4"!!(" # !$ # ! ! 0" & / " "# % #" # ! ! " ""# $&,4# %# !4" 3 !!" ""# # !$ "%""$& 27 dc recommended operating conditions & <3)85u+ ## 2"# # "" & *& b0 #nj ++ k&j" # # 2" *#& .& #n3&j" # # 2" *#& )& b0 # # #! t # & 28 capacitance (ta = 25c, f = 1 mhz) "#! "##! " " $ "#t # & item symbol ratings unit 0 0 0 $/ 0 1k %?80 !! e?f0 0 " 0 0 !! %?8870 0 " @? . b %=7@7? d! 1 # %;?>7 d! symbol parameter min typ max unit 0 !! " 0 @6 @>7 8? 0 0 b ? ? ? 0 $2 $ 20 ?>+0 !! <0 !! e?8 8 0 $ $ "0 %?8 f ! 0 $/ j?0 < > , ! $1 $ g1 ! 0 1k j?0 < @? , 109 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 29 dc and operating characteristics 29.1 common & / $"( #+ @ "##! # %$+ @ & 30 ac operating conditions 30.1 test conditions (test load and test input/output reference) $ (?80 !! %?80 $ (f $ (?7+0 !! 1 , f?@ (! j7?, figure 30.1 par mode execution and exit item symbol test conditions min typ max unit $ ' ! $ $ 0 $/ j0 0 !! %@ < @ s# 1 ' ! $ 1 !lj0 $2 4:lj0 $2 1-lj0 $2 .-lj0 $ 0 $1 j0 0 !! %@ < @ s# # 1 ! $ !!8 ! j :! ef ! $ $1 j? # @??` !lj0 $ 4:lj0 $2 0 $/ j0 $ 0 $2 <<;? # 1 "0 0 1 $ 1 j?@ # < < ?8 0 1 20 0 12 $ 12 j%?@ # @; < < 0 ! !41 $ a@ !l 0 !! %?80 4:l 0 !! %?80 1 j0 0 !! ^;?d! < < a s# ^>7d! < < 8?? s# : ! $ a @ 4:l ?80 !l 0 !! %?80 1 j0 0 !! ^;?d! fg;a ' < < a s# @g8a ' < < a @g;a ' < < a ^>7d! fg;a ' < < @6? s# @g8a ' < < @7? @g;a ' < < @;? 50 dout 30pf z0= 50 vtt = 0.5 x v ddq september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 110 preliminary 30.2 asynchronous ac characteristics 0 !! j@6_8?0 # jc;?>7d! f !" <6# "#2" "0 5"! #& symbol parameter speed bins unit min max read :! : ! 6? < ! : ! 87 < ## # # < 6? # # < 8? !1 ! 1 < 6? 1- 1 - 01 < f7 a# kal al# < f7 w ! "%w1 @? < a w kal al- "%w1 7 < 1 w 1 - "%w1 7 < !2w ! 2%w1 ? 6 a2w kal al 2%w1 ? 6 12w 1 2%w1 ? 6 12 1 2 f < write .! . ! 6? < !. ! - . =? < # 0 # 0l4 " . 6 < # # % a . ? < ## # % # 0l, ? < #2# # 2 # 0l: 6 < !# !l # 0l: @? < #. # 0- . =? < a. kal al0- . =? < . . . 77/ @ < .2 .-l2 . 7 %@ ' < .: . : ? < . : .-l ": @ < ' . . 1 f? < 2 2 . ? < 111 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 30.3 timing diagrams 94$9$# * , 7 4:lj0 $2 .-lj0 $2 .#$lj2%w & +=v b=v " # "! 2" # " 0 " " ""# 0 0 #& *& $ "0 ! 0 "" +=v'4& "# ## ;v'"& % "0 0" ! 0" 0" " "& .& @#$ # $ + j- f @-#" # " & figure 30.2 timing waveform of asynchronous read cycle table 30.1 asynchronous read ac characteristics symbol speed units symbol speed units minmax minmax :! 6? < 1 w 7< ## <6? a w 7< !1 <6? w @? < a# 4:lj0 $2 .-lj0 $2 .#$lj2%w & +=v b=v " # "! 2" # " 0 " " ""# 0 0 #& *& $ "0 ! 0 "" +=v'4& "# ## ;v'"& % "0 0" ! 0" 0" " "& .& @#$ #) $ + j- f @-#" # " & figure 30.3 timing waveform of page read cycle ta b l e 3 0 . 2 asynchronous page read ac characteristics symbol speed units symbol speed units minmax minmax :! 6? < 12 f< ## <6? 1 w 7< ! 87 < a w 7< # <8? w @? < !1 <6? !2w ?6 a# # . ! %.-l! & 2" # " 0 f 2+- 2f,-& 2" % "#2 +- #2 f,- # 22"## " -; -#" %$ " #"! #$## " - ; - % %$ "& 2" # " ##""2 +- #" f,- #" & f "#! # ! % "" 2" 2" & *& +f "#! # ! +- " 2 2" & .& "#! # ! ##0" % "" 2" & )& f( "#! # ! 2" ## & f( "#" " # 2" #2"+-f,- " " & 5& @#$ #2" $ + j- f @-#" # " & figure 30.4 timing waveform of write cycle ta b l e 3 0 . 3 asynchronous write ac characteristics f!" <6# "#2" "0 5"! #& symbol speed units symbol speed units min max min max .! 6? < # ?< !. =? < .: ?< #. =? < . f? < a. =? < 2 ?< . 77 @ < address we# d ata i n t wc t cw t aw t bw t wp t as t dh t dw high-z high-z data valid cs# t wr data out high- z high-z ub#, lb# september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 114 preliminary 94$9$:$# 7 : 4:lj0 $2 1-lj0 $2 .#$lj2%w kalh al! & 2" # " 0 f 2+- 2f,-& 2" % "#2 +- #2 f,- # 22"## " -; -#" %$ " #"! #$## " - ; - % %$ "& 2" # " ##""2 +- #" f,- #" & f "#! # ! % "" 2" 2" & *& +f "#! # ! +- " 2 2" & .& "#! # ! ##0" % "" 2" & )& f( "#! # ! 2" ## & f( "#" " # 2" #2"+-f,- " " & 5& @#$ #2" $ + j- f @-#" # " & figure 30.5 timing waveform of write cycle(2) ta b l e 3 0 . 4 asynchronous write ac characteristics (ub# & lb# controlled) f!" <6# " #2" "0 5"! #& symbol speed units symbol speed units min max min max .! 6? < # ?< !. =? < .: ?< #. =? < . f? < a. =? < 2 ?< . 77 @ < address data valid we# data in data out high-z high- z t wc t cw t bw t wp t dh t dw t wr t aw t as cs# ub#, lb# 115 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 94$9$:$# 7 d *," 4:lj0 $2 1-lj0 $2 .#$lj2%w .-l! & 2" # " 0 f 2+- 2f,-& 2" % "#2 +- #2 f,- # 22"## " -; -#" %$ "#"! #$## " - ; -2 "& 2" # " ##""2 +- #" f,- #" & f "#! # ! % "" 2" 2" & *& f "#! # ! ##0" 2" &@"# ## $ 2" "!" f+ "##! # f & .& +f "#! # ! +- " 2 2" & )& f "#! # ! - ; - " 2 2" & 5& + " #0 $ 2" "" ! f;(; "#! & figure 30.6 timing waveform of write cycle (address latch type) ta b l e 3 0 . 5 asynchronous write in synchronous mode ac characteristics & ##; $ f,-+ & *& f!" <6# "#2" "0 5"! #& symbol speed units symbol speed units min max min max # 0 6< a. =? < ## ?< . 77 8 < #2# 6< . : @< ' !# @? < # ?< !. =? < . f? < #. =? < 2 ?< we# data in t bw t wp t dh t dw data valid adv# address cs# valid t as(a) t ah(a) t css(a) t cw data out high-z 12345678910111213 clk 0 t as read latency 5 high- z t wlrl 14 t aw t adv ub#, lb# september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 116 preliminary 94$9$# * 7 , 7 -* 94$9$#$# 7 d! &c," 4:lj0 $2 1-lj0 $2 .#$lj2%w .-l! & ;2 j-$ 2" $ 3f,-+ & *& 2" # " 0 f 2+- 2f,-& 2" % "#2 +- #2 f,- # 22"## " -; -#" %$ " #"! #$## " - ; - % %$ "& 2" # " ##""2 +- #" f,- #" & f "#! # ! % "" 2" 2" & .& +f "#! # ! +- " 2 2" & )& "#! # ! ##0" % "" 2" & 5& f( "#! # ! 2" ## & f( "#" " # 2" #2"+-f,- " " & g& + " #0 $ 2" "" ! f;(; "#! & figure 30.7 timing waveform of write cycle (low adv# type) ta b l e 3 0 . 6 asynchronous write in synchronous mode ac characteristics & ;2 j-$ f,-+ & *& f!" <6# "#2" "0 5"! #& symbol speed units symbol speed units min max min max .! 6? < . : @< ' !. =? < # ?< #. =? < .: ?< a. =? < . f? < . 77 8 < 2 ?< address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high-z high- z 123456789 clk 0 read latency 5 10 11 12 13 14 t wlrl ub#, lb# 117 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 94$9$#$: 7 d! &c," 4:lj0 $2 1-lj0 $2 .#$lj2%w kalh al! & ;2 j-$ 2" $ 3 - ; -+ & *& 2" # " 0 f 2+- 2f,-& 2" % "#2 +- #2 f,- # 22"## " -; -#" %$ " #"! #$## " - ; - % %$ "& 2" # " ##""2 +- #" f,- #" & f "#! # ! % "" 2" 2" & .& +f "#! # ! +- " 2 2" & )& "#! # ! ##0" % "" 2" & 5& f( "#! # ! 2" ## & f( "#" " # 2" #2"+-f,- " " & g& + " #0 $ 2" "" ! f;(; "#! & figure 30.8 timing waveform of write cycle (low adv# type) ta b l e 3 0 . 7 asynchronous write in synchronous mode ac characteristics & ;2 j-$ !" 2" - ; - & *& f!" <6# "#2" "0 5"! #& symbol speed units symbol speed units min max min max .! 6? < . : @< ' !. =? < # ?< #. =? < .: ?< a. =? < . f? < . 77 8 < 2 ?< address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high- z clk read latency 5 123456789 0 10 11 12 13 14 t wlrl high-z ub#, lb# september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 118 preliminary 94$9$#$9 "7 d! &c," 4:-j0 $2 1-lj0 $2 .#$lj2%w .-l! a & ;2 j-$ !" 2" $ & *& 2" # " 0 f 2+- 2f,-& 2" % "#2 +- #2 f,- # 22"## " -; -#" %$ " #"! #$## " - ; - % %$ "& 2" # " ##""2 +- #" f,- #" & f "#! # ! % "" 2" 2" & .& +f "#! # ! +- " 2 2" & )& "#! # ! ##0" % "" 2" & 5& f( "#! # ! 2" ## & f( "#" " # 2" #2"+-f,- " " & g& + " #0 $ #$ #!" 2" "" f= "## ( ; $3 "& 6& f!" <6# "#2" "0 5"! #& figure 30.9 timing waveform of multiple write cycle (low adv# type) ta b l e 3 0 . 8 asynchronous write in synchronous mode ac characteristics & ;2 j-$ !" 2" f,-+ & *& f!" <6# "#2" "0 5"! #& symbol speed units symbol speed units min max min max .! 6? < .2 7 %@ ' < !. =? < # ?< #. =? < .: ?< a. =? < . f? < . 77 8 < 2 ?< address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high-z high-z 123456789 clk 0 10 11 12 13 t wc t as t wr data valid t dh t dw t whp t wp t cw t aw t bw 14 ub#, lb# 119 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 31 ac operating conditions 31.1 test conditions (test load and test input/output reference) $ (?80 !! %?80 $ (f $ (?7+0 !! 1 , f@@ (! jf?, figure 31.1 ac output load circuit 50 dout 30pf z0= 50 vtt = 0.5 x v ddq september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 120 preliminary 31.2 synchronous ac characteristics .&j ++ <&6w*&j <3)85u+ '4"!!'"+ / e $<gg'=7& 31.3 timing diagrams 9#$9$# -* / e" , 7 j7 a j;4:lj0 $2 parameter list symbol speed units min max burst operation (common) ! '! @7 8?? a ! a! < 87?? # % # 0l, a #a ?< # 2 # 0l: a #2a 6< # 0l # 0 7< # 0l2 # 02 6< !l ! ': a !a 7< a - / "# 0l, a-# 0 6< a / "# 0l, a# 0 @8 < !l "2 ! ' ! 2 6< !l2 . !2 77 < # 0l2 . # 2 << ! .#$l " . <@? # 0l, .#$l " #. <@? ! '.#$l2 .2 <@8 ! % .#$l2%w .w <6 burst read operation kal al- - ! ' a- @< ' 1 - - ! ' 1- @< ' kal al0 "%w1 a w 7< 1 - "%w1 1 w 7< ! ': - 1 ! <@? 1 2 12 f< a - ! '1 2%w 2w <@? ! % 1 2%w !2w <6 1 1 2%w 12w <6 kal al 1 2%w a2w <6 burst write operation .-l % ! ! ' .- 7< .-l2 ! ! ' .-2 7< .-l2 . .2 7< kal al % ! ' a 7< kal al2 ! ' a2 7< a 4' % ! ' a4 6< a 4' 2 ! ' a42 6< % ! ' 7< 2 ! ' 2! f< 121 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary figure 31.2 timing waveform of basic burst operation table 31.1 burst operation ac characteristics symbol speed units symbol speed units min max min max @7 8?? #a ?< a! < 87?? #2a 6< # 0 7< !a 7< # 02 6< a-# 0 6< 123456789101112131415 adv# address clk t advs t advh t as(b) t ah(b) t 0 t beadv don?t care valid valid burst command clock burst read end clock data out dq0 dq1 dq2 dq3 data in d0 d1 d3 d0 d2 t beadv burst write end clock cs# t css(b) t bc undefined september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 122 preliminary 9#$9$: -* / , 7 9#$9$:$# , j7 a j ; .j " .-lj0 $2 4:lj0 $2 !l ! a : & 2%# " % "## $ 0"# %# ""#""# &/ 2%# " , j # % ! & *& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " & .& '" "#" # 2 " 2 j- " & %# "##! "# "#" & )& #+$ "! + # % 0 *&5p#& figure 31.3 timing waveform of burst read cycle (1) ta b l e 3 1 . 2 burst read ac characteristics symbol speed units symbol speed units minmax minmax !2 7< 12w <6 a- @< ' a2w <6 1- @< ! <@? a w 7< 12 f< 1 w 7< . <@? 2w <@? .2 <@8 !2w <6 .w <6 123456789101112131415 adv# address cs# data out oe# clk dq0 dq1 dq2 dq3 t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl t wz t chz t ohz t bhz t cshp t wl t wh t beadv t bc lb#, ub# undefined 123 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary j7 a j ; .j " .-lj0 $2 4:lj0 $2 !l "2 ! a : & 2%# " % "## $ 0"# %# ""#""# &/ 2%# " , j # % ! & *& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " & .& '" "#" # 2 " 2 j- " & %# "##! "# "#" & )& # "0 !" %# "2" " +-2"###"% $ "##" 2 j- ##& 5& #+$ "! + # % 0 *&5p#& figure 31.4 timing waveform of burst read cycle (2) ta b l e 3 1 . 3 burst read ac characteristics symbol speed units symbol speed units minmax minmax a- @< ' ! <@? 1- @< 12 f< a w 7< . <@? 1 w 7< #. <@? 2w <@? .2 <@8 1234567891011121314 adv# address cs# data out oe# clk dq0 dq1 dq2 dq3 t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl t awl t wh t beadv t bc lb#, ub# undefined 15 september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 124 preliminary j7 a j ; .j " .-lj0 $2 4:lj0 $2 & af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " & *& '" "#" # 2 " 2 j- " & %# "##! "# "#" & .& #+$ "! + # % 0 *&5p#& figure 31.5 timing waveform of burst read cycle (3) ta b l e 3 1 . 4 burst read ac characteristics symbol speed units symbol speed units min max min max a- @< ' ! <@? 1- @< 12 f< a w 7< . <@? 1 w 7< #. <@8 adv# address cs# data out oe# clk dq0 dq1 dq2 t cd valid latency 5 t advs t advh t as(b) t ah(b) t css(b) t t oh don?t c are dq3 1234567891011121314 t bel t oel t blz t olz wait# high-z 0 t wl t wh t bc lb#, ub# undefined 125 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 9#$9$:$# 7 , j7 a j ; .j " 1-lj0 $2 4:lj0 $2 !l ! a . & 2%# " % "## $ 0"# %# ""#""# &/ 2%# " , j # % ! & *& '" "#" # 2 " 2 j- " & %# "##! "# "#" & .& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " )& *"#!# %$ - ; -& 5& #+$ "! + # % 0 *&5p#& figure 31.6 timing waveform of burst write cycle (1) ta b l e 3 1 . 5 burst write ac characteristics symbol speed units symbol speed units minmax minmax !2 7< .2 7< a 7< 7< a2 7< 2! f< a4 6< . <@? a42 6< .2 <@8 .- 7< .w <6 .-2 7< 12345678910111213 adv# address cs# data in we# clk d0 d1 d2 d3 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc wait# 0 t wes t weh t ds t dhc don?t ca re t bms t bmh latency 5 high-z t wl t wh valid t bs t bh d0 t whp t cshp t wz t wl latency 5 valid valid t wh t beadv t bc lb#, ub# september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 126 preliminary j7 a j ; .j " 1-lj0 $2 4:lj0 $2 !l "2 ! a . & 2%# " % "## $ 0"# %# ""#""# &/ 2%# " , j # % ! & *& '" "#" # 2 " 2 j- " & %# "##! "# "#" & .& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " )& *"#!# %$ - ; -& 5& # "0 !" %# "2" " +-2"###"% $ "##" 2 j- ##& g& #+$ "! + # % 0 *&5p#& figure 31.7 timing waveform of burst write cycle (2) ta b l e 3 1 . 6 burst write ac characteristics symbol speed units symbol speed units min max min max a 7< .2 7< a2 7< 7< a4 6< 2! f< a42 6< . <@? .- 7< #. <@? .-2 7< .2 <@8 12345678910111213 adv address cs# data in we# clk d0 d1 d2 d3 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc wait# 0 t wes t weh t ds t dhc don?t ca re t bms t bmh latency 5 high-z t wl t wh valid t bs t bh d0 t whp t awl latency 5 valid valid t wh t beadv t bc lb#, ub# 127 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 9#$9$9 -* / -", 7 j7 a j ; .j " .-lj0 $2 4:lj0 $2 & 2%# " % "## $ 0"#%# ""#""# & *& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " .& '" "#" # 2 " 2 j- " & %# "##! "# "#" & )& %## "# % 0 *&5p#& figure 31.8 timing waveform of burst read stop by cs# ta b l e 3 1 . 7 burst read stop ac characteristics symbol speed units symbol speed units min max min max a# 0 @8 < ! <@? ! 2 6< 12 f< !2 7< !2w <6 a- @< ' . <@? 1- @< .2 <@8 a w 7< .w <6 1 w 7< 1234567891011121314 adv# address cs# data oe# clk dq0 t cd don?t c are valid latency 5 valid t advs t advh t as(b) t ah(b) t css(b) t t oh t chz wait# t bel t oel t blz t olz t cslh t cshp high-z 0 high- z t wl t wh t wz t wl dq1 t bsadv lb#, ub# undefined september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 128 preliminary 9#$9$@ -* / 7 -", 7 j7 a j ; .j " 1-lj0 $2 4:lj0 $2 & 2%# " % "## $ 0"#%# ""#""# & *& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " .& '" "#" # 2 " 2 j- " & %# "##! "# "#" & )& %## "# % 0 *&5p#& figure 31.9 timing waveform of burst write stop by cs# ta b l e 3 1 . 8 burst write stop ac characteristics symbol speed units symbol speed units min max min max a# 0 @8 < .2 7< ! 2 6< 7< !2 7< 2! f< a 7< . <@? a2 7< .2 <@8 .- 7< .w <6 .-2 7< 12345678910111213 adv# address cs# data in we# clk d0 d1 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc wait# 0 t wes t weh t ds valid d0 t cshp t cslh high-z high-z t wl t wh t wz t wl latency 5 latency 5 t wh d1 d2 don?t ca re t whp t bsadv t bs t bh lb#, ub# 129 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary 9#$9$( -* / - " , 7 j7 a j ; .j " .-lj0 $2 4:lj0 $2 & @ ""# " %# " 2"% ## &" %# ## " b,-" "0 # " 3v&@ ""# #! ## 2"% "#& *& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " .& " ## " b,-" "0 #h=" 3v b,-2 "0 #h;23v&@b,-#$#2 " ## " 0"# 2"% ##" & )& #+$ "! + # % 0 *&5p#& figure 31.10 timing waveform of burst read suspend cycle (1) ta b l e 3 1 . 9 burst read suspend ac characteristics symbol speed units symbol speed units min max min max a- @< ' 2w <@? 1- @< 12w <6 a w 7< . <@? 1 w 7< .2 <@8 ! <@? .w <6 12 f< 123456 7891 011 adv# address cs# data out oe# clk dq0 dq1 dq2 t cd valid latency 5 t hz t advs t advh t as(b) t ah(b) t css(b) t don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl dq1 t wz t ohz t olz dq3 high-z t bc t oh lb#, ub# undefined september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 130 preliminary 32 transition timing waveform between read and write j7 a j ; .j " 4:lj0 $2 & 2%# " % "## $ 0"# %# ""#""# &/ 2%# " , j # % ! & *& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " .& '" "#" # 2 " 2 j- " & %# "##! "# "#" & )& #+$ "! + # % 0 *&5p#& figure 32.1 synchronous burst read to asynchronous write (address latch type) table 32.1 burst read to asynchronous wr ite (address latch type) ac characteristics symbol speed units symbol speed units min max min max a-# 0 6< . : @< ' 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 2 1 dq1 dq3 dq2 we# t css(a) data in t dh t dw data valid high- z high-z t as(a) t ah(a) t beadv t as read laten cy 5 0 t wp t wlrl t cw t aw t bw t bc wait# high-z t wh t wl t wz high-z t adv lb#, ub# 131 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary j7 a j;4:lj0 $2 & 2%# " % "## $ 0"# %# ""#""# &/ 2%# " , j # % ! & *& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " .& '" "#" # 2 " 2 j- " & %# "##! "# "#" & )& #+$ "! + # % 0 *&5p#& figure 32.2 synchronous burst read to asynchronous write (low adv# type) ta b l e 3 2 . 2 burst read to asynchronous write (low adv# type) ac characteristics symbol speed units symbol speed units min max min max a-# 0 6< . : @< ' 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz t css(b) t t oh don?t ca re t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq2 we# data in t dh t dw data valid high-z high-z t beadv t aw t cw t wp t bw t as t wr valid addr ess read late ncy 5 t wlrl wait# high-z t wh t wl t wz dq3 t bc high-z lb#, ub# september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 132 preliminary j7 a j;4:lj0 $2 & 2%# " % "## $ 0"# %# ""#""# &/ 2%# " , j # % ! & *& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " .& '" "#" # 2 " 2 j- " & %# "##! "# "#" & )& #+$ "! + # % 0 *&5p#& figure 32.3 asynchronous write (address latch type) to synchronous burst read timing ta b l e 3 2 . 3 asynchronous write (address latch type) to burst read ac characteristics symbol speed units symbol speed units min max min max . : @< ' 12345678910111213 1920 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(a) t t oh t bel t oel t advs t advh t as(a) t ah(a) 14 15 16 17 18 0 dq1 dq3 dq2 we# t css(b) data in high- z t as(b) t ah(b) t wp t bw t as read latency 5 t dh t dw data valid don?t care don?t care t aw t cw t adv t wlrl wait# high- z t wh t wl t wz t bc lb#, ub# 133 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary j7 a j;4:lj0 $2 & 2%# " % "## $ 0"# %# ""#""# &/ 2%# " , j # % ! & *& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " .& '" "#" # 2 " 2 j- " & %# "##! "# "#" & )& #+$ "! + # % 0 *&5p#& figure 32.4 asynchronous write (low adv# type) to synchronous burst read timing ta b l e 3 2 . 4 asynchronous write (low adv# type) to burst read ac characteristics symbol speed units symbol speed units min max min max . : @< ' # 2 < 12345678910111213 1920 adv# address cs# data out oe# clk dq0 t cd latency 5 t hz valid t t oh t bel t oel t advs t advh 14 15 16 17 18 0 dq1 dq3 dq2 we# t css(b) data in high- z t as(b) t ah(b) t as t dh t dw data valid don?t care t aw t cw valid t wr t wp t bw t wc t adhp read latency 5 t wlrl wait# high- z t wh t wl t wz t bc lb#, ub# september 8, 2005 s75ws_02_a1 s75ws256nxx based mcps 134 preliminary j7 a j;4:lj0 $2 & 2%# " % "## $ 0"# %# ""#""# &/ 2%# " , j # % ! & *& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " .& '" "#" # 2 " 2 j- " & %# "##! "# "#" & )& #+$ "! + # % 0 *&5p#& figure 32.5 synchronous burst read to synchronous burst write timing ta b l e 3 2 . 5 asynchronous write (low adv# type) to burst read ac characteristics symbol speed units symbol speed units min max min max a-# 0 6< high- z 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq3 dq2 we# t css(b) data in high- z high-z t beadv 0 t bc t as(b) t ah(b) d1 d3 d2 high-z d0 wait# t wh t wl t wz latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh lb#, ub# 135 s75ws256nxx based mcps s75ws_02_a1 se ptember 8, 2005 preliminary j7 a j;4:lj0 $2 & 2%# " % "## $ 0"# %# ""#""# &/ 2%# " , j # % ! & *& af @;2 f; f; n0"% "0 %$+-2 " j-2 " af @=" f= n0"% "0 %$; $3 af @=" 3v fv n ? "0 %$+-" " .& '" "#" # 2 " 2 j- " & %# "##! "# "#" & )& #+$ "! + # % 0 *&5p#& figure 32.6 synchronous burst write to synchronous burst read timing ta b l e 3 2 . 6 asynchronous write (low adv# type) to burst read ac characteristics symbol speed units symbol speed units min max min max a-# 0 6< high-z 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 we# t css(b) data in high-z t beadv 0 t bc t as(b) t ah(b) d1 d2 wait# t wh t wl latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh d3 d0 dq0 dq1 dq3 dq2 high- z lb#, ub# september 8, 2005 s75ws_02_a0 s75ws-n based mcps 136 advance information 33 revisions revision a0 (february 17, 2005) $ : revision a2 (september 8, 2005) j : 89:%/ - j k >?42& e k " " & k " "3e" " k /+ k k * # ,-#?>; ' d+;* : -:'7-; * k colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reac tion control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch co ntrol in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion llc will not be liable to you and/or any third party for any claims or damages arising in connection with above- mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporatin g safety design measures into your facility and equipment such as redundancy, fire protection, and prev ention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on ex- port under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government enti ty will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty , express, implied, or stat utory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ?2005 spansion llc. all rights reserved. spansion, the spansion logo, and mirrorbit are trademarks of spansion llc. o ther company and product names used in this publication are for id entification purposes only and may be tr ademarks of their respective companies. |
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